Nuova ricerca

TOMMASO ZANOTTI

Dottorando presso: Dipartimento di Ingegneria "Enzo Ferrari"


Home | Curriculum(pdf) |


Pubblicazioni

2021 - Advanced Data Encryption ​using 2D Materials [Articolo su rivista]
Wen, Chao; Li, Xuehua; Zanotti, Tommaso; Puglisi, Francesco Maria; Shi, Yuanyuan; Saiz, Fernan; Antidormi, Aleandro; Roche, Stephan; Zheng, Wenwen; Liang, Xianhu; Hu, Jiaxin; Duhm, Steffen; Roldan, Juan B.; Wu, Tianru; Chen, Victoria; Pop, Eric; Garrido, Blas; Zhu, Kaichen; Hui, Fei; Lanza, Mario
abstract


2021 - Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise based on Resistive Memories [Relazione in Atti di Convegno]
Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
abstract

In-memory computing architectures based on Resistive random access memory technologies (RRAM) are a promising candidate for the development of ultra-low power hardware accelerators that could enable the deployment of deep neural networks inference algorithms on energy constrained devices at the edge of the communication network. However, the study of the reliability of such circuits is non-trivial due to the intrinsic RRAM devices nonlinearity and stochasticity. For instance, RRAM devices are subject not only to device-to-device and cycle-to-cycle resistance variations but also to Random Telegraph Noise which introduces additional time dependent resistance fluctuations that could result in reduced circuit performance. Previous studies exploited simplified statistical models to show that such device nonidealities may reduce the classification accuracy even when binarized neural networks are employed. However, a circuit reliability analysis based on full circuit-level simulations is still missing. In this work, we develop and train a low-bit precision neural network which employs binary weights and 4-bits activations. We further analyze the impact of RRAM nonidealities (e.g., variability and Random Telegraph Noise) on the classification accuracy by means of full circuit-level simulations enabled by a physics-based RRAM compact model, calibrated on experimental data from the literature. Results show that combining binary weights with low-precision activations allows retaining software-level accuracy even in the presence of Random Telegraph Noise and weight variability.


2021 - Random Telegraph Noise in Metal-Oxide Memristors for True Random Number Generators: A Materials Study [Articolo su rivista]
Li, X.; Zanotti, T.; Wang, T.; Zhu, K.; Puglisi, F. M.; Lanza, M.
abstract

Some memristors with metal/insulator/metal (MIM) structure have exhibited random telegraph noise (RTN) current signals, which makes them ideal to build true random number generators (TRNG) for advanced data encryption. However, there is still no clear guide on how essential manufacturing parameters like materials selection, thicknesses, deposition methods, and device lateral size can influence the quality of the RTN signal. In this paper, an exhaustive statistical analysis on the quality of the RTN signals produced by different MIM-like memristors is reported, and straightforward guidelines for the fabrication of memristors with enhanced RTN performance are presented, which are: i) Ni and Ti electrodes show better RTN than Au electrodes, ii) the 50 μm × 50 μm devices show better RTN than the 5 μm × 5 μm ones, iii) TiO2 shows better RTN than HfO2 and Al2O3, iv) sputtered-oxides show better RTN than ALD-oxides, and v) 10 nm thick oxides show better RTN than 5 nm thick oxides. The RTN signals recorded have been used as entropy sources in high-throughput TRNG circuits, which have passed the randomness tests of the National Institute of Standards and Technology. The work can serve as a useful guide for materials scientists and electronic engineers when fabricating MIM-like memristors for RTN applications.


2021 - STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing [Articolo su rivista]
De Rose, Raffaele; Zanotti, Tommaso; Maria Puglisi, Francesco; Crupi, Felice; Pavan, Paolo; Lanuzza, Marco
abstract

Spin-transfer torque magnetic tunnel junction (STT-MTJ) technology is an attractive solution for designing non-volatile Logic-in-Memory (LIM) architectures. This work explores a smart material implication (SIMPLY) LIM scheme based on nanoscale STT-MTJs. The SIMPLY architecture is benchmarked against the conventional material implication (IMPLY) logic. Obtained results prove that for similar performance the STT-MTJ based SIMPLY scheme ensures more reliable operation (i.e., lower error rate by more than three orders of magnitude) and an energy saving of -70% than its IMPLY counterpart, at the only cost of minimal area overhead.


2020 - A Smart Logic-in-Memory Architecture for Low-Power non-von Neumann Computing [Articolo su rivista]
Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
abstract

Low-power smart devices are becoming pervasive in our world. Thus, relevant research efforts are directed to the development of innovative low power computing solutions that enable in-memory computations of logic-operations, thus avoiding the von Neumann bottleneck, i.e., the known showstopper of traditional computing architectures. Emerging non-volatile memory technologies, in particular Resistive Random Access memories, have been shown to be particularly suitable to implement logic-in-memory (LIM) circuits based on the material implication logic (IMPLY). However, RRAM devices nonidealities, logic state degradation, and a narrow design space limit the adoption of this logic scheme. In this work, we use a physics-based compact model to study an innovative smart IMPLY (SIMPLY) logic scheme which exploits the peripheral circuitry embedded in ordinary IMPLY architectures to solve the mentioned reliability issues, drastically reducing the energy consumption and setting clear design strategies. We then use SIMPLY to implement a 1-bit full adder and compare the results with other LIM solutions proposed in the literature.


2020 - Circuit Reliability Analysis of In-Memory Inference in Binarized Neural Networks [Relazione in Atti di Convegno]
Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
abstract


2020 - Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise [Relazione in Atti di Convegno]
Zanotti, T.; Puglisi, F. M.; Pavan, P.
abstract

The Logic-in-Memory paradigm is considered a promising solution for improving the energy efficiency and computing power of architectures aimed at low power and/or data-intensive applications. Among in-memory computing enabling technologies, emerging non-volatile memories (e.g., RRAMs) are promising as they offer BEOL integration and small feature size. Several studies have shown that IMPLY architectures based on RRAM devices and the material implication logic enable the efficient computation of logic operations using the RRAM device both as storing and computing element. However, RRAM devices non-idealities introduce important circuit reliability issues, that are frequently neglected, thus undermining the circuit functionality. In this work, we use a physics-based compact model calibrated on experimental data to simulate the IMPLY operation performed on a crossbar array including line parasitic effects and RRAM devices non-idealities. We then introduce a novel smart scheme, SIMPLY, and show the circuit reliability improvement.


2020 - Reconfigurable Smart In-Memory Computing Platform Supporting Logic and Binarized Neural Networks for Low-Power Edge Devices [Articolo su rivista]
Zanotti, T.; Puglisi, F. M.; Pavan, P.
abstract

Edge computing has been shown to be a promising solution that could relax the burden imposed onto the network infrastructure by the increasing amount of data produced by smart devices. However, reconfigurable ultra-low power computing architectures are needed. RRAM devices together with the material implication logic (IMPLY) are a promising solution for the development of low-power reconfigurable logic-in-memory (LiM) hardware. Nevertheless, traditional approaches suffer from several issues introduced by the circuit topology and device non-idealities. Recently, SIMPLY, a smart LiM architecture based on the IMPLY, has been proposed and shown to solve the common issues of traditional architectures. Here, we use a physics-based RRAM compact model calibrated on three RRAM technologies to further analyze the performance of SIMPLY in typical operating conditions, when the repeated execution of logic operation on the same group of devices is considered. The results show that, compared to the conventional IMPLY architecture, SIMPLY spares more than 40% of the high voltage pulses on average even when complex operations are considered (e.g., the 1-bit half adder). We also show how SIMPLY can implement the set of operations required for the implementation of Binarized Neural Networks (BNN) and benchmark its performance against other memristor-based BNN in-memory accelerator from the literature. The results suggest that our approach is more than two orders of magnitude efficient compared to the state of the art reconfigurable in-memory computing approach and could potentially reach the performance of specialized BNN analog hardware accelerators with appropriate device-circuit co-design strategies.


2020 - Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays [Articolo su rivista]
Zanotti, T.; Zambelli, C.; Puglisi, F. M.; Milo, V.; Perez, E.; Mahadevaiah, M. K.; Ossorio, O. G.; Wenger, C.; Pavan, P.; Olivo, P.; Ielmini, D.
abstract

Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25-μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.


2020 - Reliability-Aware Design Strategies for Stateful Logic-in-Memory Architectures [Articolo su rivista]
Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
abstract


2020 - Smart Logic-in-Memory Architecture For Ultra-Low Power Large Fan-In Operations [Relazione in Atti di Convegno]
Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
abstract

The need for processing the continuously growing amount of data that is produced every day is promoting research for the development of energy-efficient non-von Neumann computing architectures. Over the last decade, resistive RAM (RRAM) devices together with material implication logic (IMPLY) were proposed as a promising solution for the development of low-power logic-in-memory (LIM) circuits. Still, the high design complexity and the low reliability of these circuits are hindering their practical realization. It is only recently that a new smart IMPLY architecture, named SIMPLY, was proposed and shown to drastically improve circuit reliability and energy efficiency of IMPLY-based LIM circuits. In this work, we introduce a new smart operation, called sFALSE, enabled by the SIMPLY architecture, and verify its feasibility using a physics-based RRAM compact model calibrated on three different technologies. We highlight the significant advantage of the proposed solution vs. ordinary IMPLY architecture in terms of energy reduction, especially for large fan-in logic operations (e.g., n-bits NAND and EXOR).


2019 - Circuit reliability of low-power rram-based logic-in-memory architectures [Relazione in Atti di Convegno]
Zanotti, T.; Puglisi, F. M.; Pavan, P.
abstract

Logic circuits based on Resistive RAM (RRAM) devices and the material implication logic (IMPLY) are promising solutions for low-power logic-in-memory (LiM) architectures. Still, their diffusion is limited by their high design complexity resulting from device and circuit non-idealities. These non-idealities are usually overlooked in the design phase when using simplified RRAM models, thus leading to unreliable designs. In this work, we derive correct design strategies for reliability of RRAM-based LiM circuits and quantitatively evaluate circuit performances using a physics-based compact model.


2019 - SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model [Relazione in Atti di Convegno]
Puglisi, F. M.; Zanotti, T.; Pavan, P.
abstract

In this work, we introduce a new RRAM-based Smart IMPLY (SIMPLY) logic scheme with unique benefits for low-power systems and verify its feasibility and advantages by means of circuit simulations allowing appropriate device/circuit requirements co-design. Differently from previous works, we use a physics-based compact model of RRAM devices able to reproduce both the ultrafast AC and the DC behavior, accounting for the intrinsic variability of the resistive states, the occurrence of Random Telegraph Noise, and the logic state degradation. The proposed scheme strongly alleviates the issue of logic state degradation, breaks the trade-off between the choice of VSET and VCOND, and allows saving energy up to a factor of ~230 requiring minimum area overhead.


2019 - Unimore Resistive Random Access Memory (RRAM) Verilog-A Model 1.0.0 [Software]
PUGLISI, Francesco Maria; ZANOTTI, TOMMASO; PAVAN, Paolo
abstract

The Unimore RRAM Verilog-A model is a physics-based compact model of bipolar RRAM which includes cycle-to-cycle variability, thermal effects, self-heating, and multilevel Random Telegraph Noise (RTN). The model considers both the quasi-ohmic charge transport along the conductive filament and the trap-assisted tunneling transport in the dielectric barrier. The reset/set operations dynamics is modeled with differential equations considering the field-driven oxygen ions drift and recombination during reset (i.e., barrier growth), and the field accelerated bond breakage during set (i.e., barrier collapse). The temperature dynamics is, likewise, modeled with differential equations that enable accurate predictions also when using very short pulses. Thus, the model enables the advanced design of circuits for many applications such as Memory, Neuromorphic Circuits, RRAM-based Neural Networks, Logic-In-Memory Systems, Physical Unclonable Functions, True Random Number Generators and others.