TOMMASO ZANOTTI Dottorando presso: Dipartimento di Ingegneria "Enzo Ferrari" |

Home | Curriculum(pdf) |

## Pubblicazioni

**2021**
- Advanced Data Encryption using 2D Materials
[Articolo su rivista]

Wen, Chao; Li, Xuehua; Zanotti, Tommaso; Puglisi, Francesco Maria; Shi, Yuanyuan; Saiz, Fernan; Antidormi, Aleandro; Roche, Stephan; Zheng, Wenwen; Liang, Xianhu; Hu, Jiaxin; Duhm, Steffen; Roldan, Juan B.; Wu, Tianru; Chen, Victoria; Pop, Eric; Garrido, Blas; Zhu, Kaichen; Hui, Fei; Lanza, Mario

abstract

**2021**
- Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise based on Resistive Memories
[Relazione in Atti di Convegno]

Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo

abstract

**2021**
- Random Telegraph Noise in Metal-Oxide Memristors for True Random Number Generators: A Materials Study
[Articolo su rivista]

Li, X.; Zanotti, T.; Wang, T.; Zhu, K.; Puglisi, F. M.; Lanza, M.

abstract

**2021**
- STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing
[Articolo su rivista]

De Rose, Raffaele; Zanotti, Tommaso; Maria Puglisi, Francesco; Crupi, Felice; Pavan, Paolo; Lanuzza, Marco

abstract

**2020**
- A Smart Logic-in-Memory Architecture for Low-Power non-von Neumann Computing
[Articolo su rivista]

Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo

abstract

**2020**
- Circuit Reliability Analysis of In-Memory Inference in Binarized Neural Networks
[Relazione in Atti di Convegno]

Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo

abstract

**2020**
- Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise
[Relazione in Atti di Convegno]

Zanotti, T.; Puglisi, F. M.; Pavan, P.

abstract

**2020**
- Reconfigurable Smart In-Memory Computing Platform Supporting Logic and Binarized Neural Networks for Low-Power Edge Devices
[Articolo su rivista]

Zanotti, T.; Puglisi, F. M.; Pavan, P.

abstract

**2020**
- Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays
[Articolo su rivista]

Zanotti, T.; Zambelli, C.; Puglisi, F. M.; Milo, V.; Perez, E.; Mahadevaiah, M. K.; Ossorio, O. G.; Wenger, C.; Pavan, P.; Olivo, P.; Ielmini, D.

abstract

**2020**
- Reliability-Aware Design Strategies for Stateful Logic-in-Memory Architectures
[Articolo su rivista]

Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo

abstract

**2020**
- Smart Logic-in-Memory Architecture For Ultra-Low Power Large Fan-In Operations
[Relazione in Atti di Convegno]

Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo

abstract

**2019**
- Circuit reliability of low-power rram-based logic-in-memory architectures
[Relazione in Atti di Convegno]

Zanotti, T.; Puglisi, F. M.; Pavan, P.

abstract

**2019**
- SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model
[Relazione in Atti di Convegno]

Puglisi, F. M.; Zanotti, T.; Pavan, P.

abstract

**2019**
- Unimore Resistive Random Access Memory (RRAM) Verilog-A Model 1.0.0
[Software]

PUGLISI, Francesco Maria; ZANOTTI, TOMMASO; PAVAN, Paolo

abstract