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Paolo PAVAN

Professore Ordinario
Dipartimento di Ingegneria "Enzo Ferrari"

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Pubblicazioni

2024 - Correlating Interface and Border Traps With Distinctive Features of C–V Curves in Vertical Al$_{\text{2}}$O$_{\text{3}}$/GaN MOS Capacitors [Articolo su rivista]
Zagni, Nicolo'; Fregolent, Manuel; Verzellesi, Giovanni; Marcuzzi, Alberto; Santi, Carlo De; Meneghesso, Gaudenzio; Zanoni, Enrico; Treidel, Eldad Bahat; Brusaterra, Enrico; Brunner, Frank; Hilt, Oliver; Meneghini, Matteo; Pavan, Paolo
abstract

In this article, we present an analysis of the correlation between interface traps (ITs) and border traps (BTs) on distinctive features of C – V curves in vertical Al 2 O 3 /gallium-nitride (GaN) MOS capacitors. First, pulsed C – V curves were characterized during the application of quiescent gate bias stresses of different magnitudes and signs. This characterization revealed four main distinctive features: 1) rightward rigid shift; 2) leftward rigid shift; 3) decrease of the Δ C – Δ V slope; and 4) formation of a hump in a gate bias range before the accumulation of electrons at the oxide/semiconductor interface. By means of a combined experimental/simulation analysis, these features were univocally attributed to specific ITs or BTs in the overall trap distribution. The simulation-aided analysis enhances the physical understanding of the C – V curves features and increases the dependability of the adopted IT measurement technique, allowing for a more rapid process optimization and device technology development.

2024 - Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD [Articolo su rivista]
Zagni, Nicolo'; Fregolent, Manuel; Del Fiol, Andrea; Favero, Davide; Bergamin, Francesco; Verzellesi, Giovanni; De Santi, Carlo; Meneghesso, Gaudenzio; Zanoni, Enrico; Huber, Christian; Meneghini, Matteo; Pavan, Paolo
abstract

Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications. Being still in an early development phase, vertical GaN devices are yet to be fully optimized and require careful studies to foster their development. In this work, we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs (TMOS’s) provided by TCAD simulations, enhancing the dependability of the adopted process optimization approaches. Specifically, two different TMOS devices are compared in terms of transfer-curve hysteresis (H) and subthreshold slope (SS), showing a ≈ 75% H reduction along with a ≈ 30% SS decrease. Simulations allow attributing the achieved improvements to a decrease in the border and interface traps, respectively. A sensitivity analysis is also carried out, allowing to quantify the additional trap density reduction required to minimize both figures of merit.

2023 - A Unified Framework to Explain Random Telegraph Noise Complexity in MOSFETs and RRAMs [Relazione in Atti di Convegno]
Vecchi, S.; Pavan, P.; Puglisi, F. M.
abstract

2023 - ANGELS - Smart Steering Wheel for Driver Safety [Relazione in Atti di Convegno]
Amidei, A.; Rapa, P. M.; Tagliavini, G.; Rabbeni, R.; Pavan, P.; Benatti, S.
abstract

The automotive industry increasingly recognizes the importance of human-machine interaction in enhancing the driving experience and improving driver safety. Human factors, such as drowsiness and attention deficits, play a primary role in safe driving. There are several research and commercial solutions to address these issues. However, they analyze vehicle behavior and are unable to assess the driver's state in a timely manner. A novel approach to this problem is to monitor the driver's physiological signals. In this context, Photoplethysmography (PPG) is a noninvasive technique that monitors cardiac activity and can provide information regarding the driver's state. This work introduces ANGELS, an embedded system that exploits PPG signals to monitor drivers in a non-invasive way. ANGELS is a low-cost and low-power system that can be integrated into the steering wheel of a car. It acquires and processes the driver's PPG signals in real-time and enables heart rate monitoring without requiring accelerometer data to remove motion artifacts. We perform an experimental assessment using the Maserati driving simulator. ANGELS features a mean absolute error on heart rate detection of 1.19 BPM with a latency of 10 s and power consumption of only 130 mW. These results demonstrate that it is a reliable and promising solution for improving driver safety.

2023 - Driver Drowsiness Detection: A Machine Learning Approach on Skin Conductance [Articolo su rivista]
Amidei, A.; Spinsante, S.; Iadarola, G.; Benatti, S.; Tramarin, F.; Pavan, P.; Rovati, L.
abstract

The majority of car accidents worldwide are caused by drowsy drivers. Therefore, it is important to be able to detect when a driver is starting to feel drowsy in order to warn them before a serious accident occurs. Sometimes, drivers are not aware of their own drowsiness, but changes in their body signals can indicate that they are getting tired. Previous studies have used large and intrusive sensor systems that can be worn by the driver or placed in the vehicle to collect information about the driver’s physical status from a variety of signals that are either physiological or vehicle-related. This study focuses on the use of a single wrist device that is comfortable for the driver to wear and appropriate signal processing to detect drowsiness by analyzing only the physiological skin conductance (SC) signal. To determine whether the driver is drowsy, the study tests three ensemble algorithms and finds that the Boosting algorithm is the most effective in detecting drowsiness with an accuracy of 89.4%. The results of this study show that it is possible to identify when a driver is drowsy using only signals from the skin on the wrist, and this encourages further research to develop a real-time warning system for early detection of drowsiness.

2023 - Exploiting Blood Volume Pulse and Skin Conductance for Driver Drowsiness Detection [Relazione in Atti di Convegno]
Poli, A.; Amidei, A.; Benatti, S.; Iadarola, G.; Tramarin, F.; Rovati, L.; Pavan, P.; Spinsante, S.
abstract

2023 - Local electric field perturbations due to trapping mechanisms at defects: What random telegraph noise reveals [Articolo su rivista]
Vecchi, S.; Pavan, P.; Puglisi, F. M.
abstract

As devices scale closer to the atomic size, a complete understanding of the physical mechanisms involving defects in high-kappa dielectrics is essential to improve the performance of electron devices and to mitigate key reliability phenomena, such as Random Telegraph Noise (RTN). In fact, crucial aspects of defects in HfO2 are still under investigation (e.g., the presence of metastable states and their properties), but it is well known that oxygen vacancies (V(+)s) and oxygen ions (O(0)s) are the most abundant defects in HfO2. In this work, we use simulations to gain insights into the RTN that emerges when a constant voltage is applied across a TiN/(4 nm)HfO2/TiN stack. Signals exhibit different RTN properties over bias and, thus, appear to originate from different traps. Yet, we demonstrate that they can be instead promoted by the same O(0)s which change their capture (tau(c)) and emission (tau(e)) time constants with the applied bias, which, in turn, changes the extent of their electrostatic interactions with the traps that assist charge transport (V(+)s). For a certain bias, RTN is given by the modulation of the trap-assisted current at V(+)s induced by trapping/detrapping events at O(0)s, which are, in turn, influenced by the bias itself and by trapped charge at nearby O(0)s. In this work, we demonstrate that accounting for the effect of trapped charge is essential to provide accurate estimation of the RTN parameters, which allow us to retrieve information about traps and to explain key mechanisms behind complex RTN signals.

2023 - Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges [Articolo su rivista]
Zagni, Nicolo'; Puglisi, Francesco Maria; Pavan, Paolo; Alam, Muhammad Ashraful
abstract

Ferroelectric transistors (FeFETs) based on doped hafnium oxide (HfO2) have received much attention due to their technological potential in terms of scalability, highspeed, and low-power operation. Unfortunately, however, HfO2-FeFETs also suffer from persistent reliability challenges, specifically affecting retention, endurance, and variability. A deep understanding of the reliability physics of HfO2-FeFETs is an essential prerequisite for the successful commercialization of this promising technology. In this article, we review the literature about the relevant reliability aspects of HfO2-FeFETs. We initially focus on the reliability physics of ferroelectric capacitors, as a prelude to a comprehensive analysis of FeFET reliability. Then, we interpret key reliability metrics of the FeFET at the device level (i.e., retention, endurance, and variability) based on the physical mechanisms previously identified. Finally, we discuss the implications of device-level reliability metrics at both the circuit and system levels. Our integrative approach connects apparently unrelated reliability issues and suggests mitigation strategies at the device, circuit, or system level. We conclude this article by proposing a set of research opportunities to guide future development in this field.

2023 - Study of RRAM-Based Binarized Neural Networks Inference Accelerators Using an RRAM Physics-Based Compact Model [Capitolo/Saggio]
Zanotti, Tommaso; Pavan, Paolo; Maria Puglisi, Francesco
abstract

In-memory computing hardware accelerators for binarized neural networks based on resistive RAM (RRAM) memory technologies represent a promising solution for enabling the execution of deep neural network algorithms on resource-constrained devices at the edge of the network. However, the intrinsic stochasticity and nonidealities of RRAM devices can easily lead to unreliable circuit operations if not appropriately considered during the design phase. In this chapter, analysis and design methodologies enabled by RRAM physics-based compact models of LIM and mixed-signal BNN inference accelerators are discussed. As a use case example, the UNIMORE RRAM physics-based compact model calibrated on an RRAM technology from the literature, is used to determine the performance vs. reliability trade-offs of different in-memory computing accelerators: i) a logic-in-memory accelerator based on the material implication logic, ii) a mixed-signal BNN accelerator, and iii) a hybrid accelerator enabling both computing paradigms on the same array. Finally, the performance of the three accelerators on a BNN inference task is compared and benchmarked with the state of the art.

2023 - The Major Effect of Trapped Charge on Dielectric Breakdown Dynamics and Lifetime Estimation [Relazione in Atti di Convegno]
Vecchi, Sara; Padovani, Andrea; Pavan, Paolo; Puglisi, Francesco Maria
abstract

2023 - Ultra-low power logic in memory with commercial grade memristors and FPGA-based smart-IMPLY architecture [Articolo su rivista]
Benatti, L; Zanotti, T; Pavan, P; Puglisi, Fm
abstract

Reducing power consumption in nowadays computer technologies represents an increasingly difficult challenge. Conventional computing architectures suffer from the so-called von Neumann bottleneck (VNB), which consists in the continuous need to exchange data and instructions between the memory and the processing unit, leading to significant and apparently unavoidable power consumption. Even the hardware typically employed to run Artificial Intelligence (AI) algorithms, such as Deep Neural Networks (DNN), suffers from this limitation. A change of paradigm is so needed to comply with the ever-increasing demand for ultra-low power, autonomous, and intelligent systems. From this perspective, emerging memristive non-volatile memories are considered a good candidate to lead this technological transition toward the next-generation hardware platforms, enabling the possibility to store and process information in the same place, therefore bypassing the VNB. To evaluate the state of current public-available devices, in this work commercial-grade packaged Self Directed Channel memristors are thoroughly studied to evaluate their performance in the framework of in-memory computing. Specifically, the operating conditions allowing both analog update of the synaptic weight and stable binary switching are identified, along with the associated issues. To this purpose, a dedicated yet prototypical system based on an FPGA control platform is designed and realized. Then, it is exploited to fully characterize the performance in terms of power consumption of an innovative Smart IMPLY (SIMPLY) Logic-in-Memory (LiM) computing framework that allows reliable in-memory computation of classical Boolean operations. The projection of these results to the nanoseconds regime leads to an estimation of the real potential of this computing paradigm. Although not investigated in this work, the presented platform can also be exploited to test memristor-based SNN and Binarized DNNs (i.e., BNN), that can be combined with LiM to provide the heterogeneous flexible architecture envisioned as the long-term goal for ubiquitous and pervasive AI.

2022 - A Hybrid CMOS-Memristor Spiking Neural Network Supporting Multiple Learning Rules [Articolo su rivista]
Florini, Davide; Gandolfi, Daniela; Mapelli, Jonathan; Benatti, Lorenzo; Pavan, Paolo; Puglisi, Francesco Maria
abstract

Artificial intelligence (AI) is changing the way computing is performed to cope with real-world, ill-defined tasks for which traditional algorithms fail. AI requires significant memory access, thus running into the von Neumann bottleneck when implemented in standard computing platforms. In this respect, low-latency energy-efficient in-memory computing can be achieved by exploiting emerging memristive devices, given their ability to emulate synaptic plasticity, which provides a path to design large-scale brain-inspired spiking neural networks (SNNs). Several plasticity rules have been described in the brain and their coexistence in the same network largely expands the computational capabilities of a given circuit. In this work, starting from the electrical characterization and modeling of the memristor device, we propose a neuro-synaptic architecture that co-integrates in a unique platform with a single type of synaptic device to implement two distinct learning rules, namely, the spike-timing-dependent plasticity (STDP) and the Bienenstock-Cooper-Munro (BCM). This architecture, by exploiting the aforementioned learning rules, successfully addressed two different tasks of unsupervised learning.

2022 - Combining Experiments and a Novel Small Signal Model to Investigate the Degradation Mechanisms in Ferroelectric Tunnel Junctions [Relazione in Atti di Convegno]
Benatti, L.; Pavan, P.; Puglisi, F. M.
abstract

2022 - Comprehensive physics-based RRAM compact model including the effect of variability and multi-level random telegraph noise [Articolo su rivista]
Zanotti, T; Pavan, P; Puglisi, Fm
abstract

Resistive Random Access Memory (RRAM) technologies are a promising candidate for the development of more energy efficient circuits, for computing, security, and storage applications. However, such devices show stochastic behaviours that not only originate from variations introduced during fabrication, but that are intrinsic to their operation. Specifically, cycle-to-cycle variations cause the programmed resistive state to be randomly distributed, while Random Telegraph Noise (RTN) introduces random current fluctuations over time. These phenomena can easily affect the reliability and performance of RRAM-based circuits. Therefore, designing such circuits requires accurate compact models. Although several RRAM compact models have been proposed in the literature, these are rarely implemented following the programming best-practice for improving the simulator convergence, and a compact model that is able to reproduce the device characteristic including thermal effects, RTN, and variability in multiple operating conditions using a single set of parameters is still missing. Also, only a few works in the literature describe the procedure to calibrate such compact models, and even fewer address the calibration of the variability on experimental data. In this work, we extend the UniMORE RRAM physics-based compact model by developing and validating two variability models, (i) a comprehensive variability model which can reproduce the effect of cycle-to-cycle variability in multiple operating conditions, and (ii) a simplified version that requires fewer calibration data and enables to reproduce cycle-to-cycle variations in specific operating conditions. The model is implemented following Verilog-A programming best-practices and validated on data from three RRAM technologies from the literature and experimentally on TiN/Ti/HfOx/TiN devices, and the relation between experimental data and the variability model parameters is described.

2022 - Defects Motion as the Key Source of Random Telegraph Noise Instability in Hafnium Oxide [Relazione in Atti di Convegno]
Vecchi, S.; Pavan, P.; Puglisi, F. M.
abstract

Besides standard two- and multi-level Random Telegraph Noise (RTN), more complex cases of RTN are commonly reported which show peculiar current signal instabilities. The physical origin of such phenomena is typically traced back to the presence of metastable defects states, the Coulomb interaction between traps, and the possible interaction of hydrogen species with oxide defects. However, the effect of the motion of atomic species on RTN phenomena has never been brought to the picture, even though such a mechanism is extremely relevant for oxygen ions in HfO2, e.g., it guarantees resistive switching in HfO2 RRAM. In this paper, we demonstrate that complex RTN signals observed in experiments naturally emerge when considering the combination of the Coulomb field due to the trapped charge at defects together with their field-assisted motion. Strikingly, we demonstrate that multilevel RTN signals with high instability and complex time evolution, which are conventionally though to be caused by an intricate many-bodies problem involving several defects, can in fact result by the

2022 - Driver Drowsiness Detection based on Variation of Skin Conductance from Wearable Device [Relazione in Atti di Convegno]
Amidei, A.; Poli, A.; Iadarola, G.; Tramarin, F.; Pavan, P.; Spinsante, S.; Rovati, L.
abstract

2022 - Self-consistent Automated Parameter Extraction of RRAM Physics-Based Compact Model [Relazione in Atti di Convegno]
Zanotti, Tommaso; Pavan, Paolo; Puglisi, Francesco Maria
abstract

2022 - Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing [Articolo su rivista]
De Rose, R.; Zanotti, T.; Puglisi, F. M.; Crupi, F.; Pavan, P.; Lanuzza, M.
abstract

Smart material implication (SIMPLY) logic has been recently proposed for the design of energy-efficient Logic-in-Memory (LIM) architectures based on non-volatile resistive memory devices. The SIMPLY logic is enabled by adding a comparator to the conventional IMPLY scheme. This allows performing a preliminary READ operation and hence the SET operation only in the case it is actually required. This work explores the SIMPLY logic scheme using nanoscale spin-transfer torque magnetic tunnel junction (STT-MTJ) devices. The performance of the STT-MTJ based SIMPLY architecture is analyzed by varying the load resistor and applied voltages to implement both READ and SET operations, while also investigating the effect of temperature on circuit operation. Obtained results show an existing tradeoff between error rate and energy consumption, which can be effectively managed by properly setting the values of load resistor and applied voltages. In addition, our analysis proves that tracking the temperature dependence of the MTJ properties through a proportional to absolute temperature (PTAT) reference voltage at the input of the comparator is beneficial to mitigate the reliability degradation under temperature variations.

2022 - Spatially Controlled Generation and Probing of Random Telegraph Noise in Metal Nanocrystal Embedded HfO2Using Defect Nanospectroscopy [Articolo su rivista]
Ranjan, A.; Puglisi, F. M.; Molina-Reyes, J.; Pavan, P.; O'Shea, S. J.; Raghavan, N.; Pey, K. L.
abstract

Random telegraph noise (RTN) is often considered a nuisance or, more critically, a key reliability challenge for miniaturized semiconductor devices. However, this picture is gradually changing as recent works have shown emerging applications based on the inherent randomness of the RTN signals in state-of-The-Art technologies, including true random number generator and IoT hardware security. Suitable material platforms and device architectures are now actively explored to bring these technologies from an embryonic stage to practical application. A key challenge is to devise material systems, which can be reliably used for the deterministic creation of localized defects to be used for RTN generation. Toward this goal, we have investigated RTN in Au nanocrystal (Au-NC) embedded HfO2stacks at the nanoscale by combining conduction atomic force microscopy defect spectroscopy and a statistical factorial hidden Markov model analysis. With a voltage applied across the stack, there is an enhanced asymmetric electric field surrounding the Au-NC. This in turn leads to the preferential generation of atomic defects in the HfO2near the Au-NC when voltage is applied to the stack to induce dielectric breakdown. Since RTN arises from various electrostatic interactions between closely spaced atomic defects, the Au-NC HfO2material system exhibits an intrinsic ability to generate RTN signals. Our results also highlight that the spatial confinement of multiple defects and the resulting electrostatic interactions between the defects provides a dynamic environment leading to many complex RTN patterns in addition to the presence of the standard two-level RTN signals. The insights obtained at the nanoscale are useful to optimize metal nanocrystal embedded high-κ stacks and circuits for on-demand generation of RTN for emerging random number applications.

2022 - The Impact of Electrostatic Interactions between Defects on the Characteristics of Random Telegraph Noise [Articolo su rivista]
Vecchi, S.; Pavan, P.; Puglisi, F. M.
abstract

Random telegraph noise (RTN) is one of the most challenging defect-related reliability concerns in emerging HfO2-based devices due to the higher bulk defect density compared to SiO2. Despite many research efforts, the physical mechanisms determining complex signals (e.g., multilevel, anomalous, temporary RTN) are still unclear and need a deeper investigation. With this driving force, we performed physic-based kinetic Monte Carlo (kMC) simulations in a TiN/HfO2/TiN cell to directly analyze the role of defects which promote RTN, both in steady state and transient regime. The nonmonotonic trends of the ratio of the RTN dwell times with the applied bias frequently found in the literature are found to be caused by changes with the applied voltage of the preferential capture/emission source/destination of traps. The in-depth analysis sheds new light on the conventional methods for defect classification and vertical position estimation. Moreover, such source/destination changes also occur over time due to the dynamics of the local electric field, which varies with the evolution of the surrounding electrostatic landscape. Notably, the local field is given by the overlap of the applied voltage and of the trapped charge contributions, the latter being dominant at low voltages. The analysis of the Markov chains of closely spaced defects shown interdependencies and alterations of the RTN capture and emission times. A new method is proposed to include the impact of electrostatic interactions between defects on RTN.

2022 - The Relevance of Trapped Charge for Leakage and Random Telegraph Noise Phenomena [Relazione in Atti di Convegno]
Vecchi, S.; Pavan, P.; Puglisi, F. M.
abstract

The current understanding of key reliability phenomena such as leakage and Random Telegraph Noise (RTN) is still incomplete. Models exist that explain simple cases (2-level RTN), yet experimental reports showed the occurrence of complex cases (e.g., coupled RTN, anomalous and temporary RTN) that deserve deeper investigation. In this paper, we focus on the often overlooked role of trapped charge in the electrostatic coupling among defects, entailing a multi-body problem, and on the related effects on leakage and RTN. The electric field in the dielectric is found to be usually dominated by the trapped charge rather than by the applied voltage, defying common beliefs and elegantly explaining some of the aforesaid complex scenarios. We demonstrate that such defects interactions are responsible for a strong modulation of the capture and emission time constants over time. Moreover, we highlight how defects capture/emission source/destination can change with the local field and therefore with the applied voltage, which gives rise to non-monotonic trends in c/e vs. applied voltage plot. This last point reveals that the classical formula adopted for the estimation of the defects vertical position within the dielectric is oversimplified and may lead to significant errors. The results of this study advance the understanding of leakage and RTN, and can be useful for the design of applications such as low-power Physical Unclonable Functions and True Random Number Generators.

2021 - Energy-efficient non-von neumann computing architecture supporting multiple computing paradigms for logic and binarized neural networks [Articolo su rivista]
Zanotti, T.; Puglisi, F. M.; Pavan, P.
abstract

Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge com-puting. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >103 times when performing a BNN inference task with respect to a SIMPLY implementation.

2021 - Evaluation of VTH and RON Drifts during Switch-Mode Operation in Packaged SiC MOSFETs [Articolo su rivista]
Cioni, Marcello; Bertacchini, Alessandro; Mucci, Alessandro; Zagni, Nicolò; Verzellesi, Giovanni; Pavan, Paolo; Chini, Alessandro
abstract

In this paper, we investigate the evolution of threshold voltage (VTH) and on-resistance (RON) drifts in the silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) during the switch-mode operation. A novel measurement setup for performing the required on-the-fly characterization is presented and the experimental results, obtained on commercially available TO-247 packaged SiC devices, are reported. Measurements were performed for 1000 s, during which negative VTH shifts (i.e., VTH decrease) and negative RON drifts (i.e., RON decrease) were observed. To better understand the origin of these parameter drifts and their possible correlation, measurements were performed for different (i) gate-driving voltage (VGH) and (ii) off-state drain voltage (VPH). We found that VTH reduction leads to a current increase, thus yielding RON to decrease. This correlation was explained by the RON dependence on the overdrive voltage (VGS–VTH). We also found that gate-related effects dominate the parameter drifts at low VPH with no observable recovery, due to the repeated switching of the gate signal required for the parameter monitoring. Conversely, the drain-induced instabilities caused by high VPH are completely recoverable within 1000 s from the VPH removal. These results show that the measurement setup is able to discern the gate/drain contributions, clarifying the origin of the observed VTH and RON drifts.

2021 - Investigation on VTH and RON Slow/Fast Drifts in SiC MOSFETs [Relazione in Atti di Convegno]
Cioni, M.; Bertacchini, A.; Mucci, A.; Verzellesi, G.; Pavan, P.; Chini, A.
abstract

RON and VTH drifts in TO-247 SiC packaged MOSFETs are investigated in this paper. The use of a novel on-the-fly measurement setup able to capture their variation over a 100µs to 1000s time range revealed the presence of two separated fast and slow mechanisms affecting the VTH and RON stability. Particularly, fast drain-induced mechanisms were found to negatively shift VTH, whereas no appreciable fast drifts were observed on RON. Conversely, slow drifts were found on both parameters, yielding a decrease in VTH and an RON increase. To investigate their origin, measurements were carried out for either i) different Duty Cycles and ii) several on-state current levels, proving that device self-heating (i.e., temperature increase) is responsible for the observed slow instabilities.

2021 - Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise based on Resistive Memories [Relazione in Atti di Convegno]
Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
abstract

In-memory computing architectures based on Resistive random access memory technologies (RRAM) are a promising candidate for the development of ultra-low power hardware accelerators that could enable the deployment of deep neural networks inference algorithms on energy constrained devices at the edge of the communication network. However, the study of the reliability of such circuits is non-trivial due to the intrinsic RRAM devices nonlinearity and stochasticity. For instance, RRAM devices are subject not only to device-to-device and cycle-to-cycle resistance variations but also to Random Telegraph Noise which introduces additional time dependent resistance fluctuations that could result in reduced circuit performance. Previous studies exploited simplified statistical models to show that such device nonidealities may reduce the classification accuracy even when binarized neural networks are employed. However, a circuit reliability analysis based on full circuit-level simulations is still missing. In this work, we develop and train a low-bit precision neural network which employs binary weights and 4-bits activations. We further analyze the impact of RRAM nonidealities (e.g., variability and Random Telegraph Noise) on the classification accuracy by means of full circuit-level simulations enabled by a physics-based RRAM compact model, calibrated on experimental data from the literature. Results show that combining binary weights with low-precision activations allows retaining software-level accuracy even in the presence of Random Telegraph Noise and weight variability.

2021 - Mechanisms Underlying the Bidirectional VT Shift After Negative-Bias Temperature Instability Stress in Carbon-Doped Fully Recessed AlGaN/GaN MIS-HEMTs [Articolo su rivista]
Zagni, Nicolo; Cioni, Marcello; Chini, Alessandro; Iucolano, Ferdinando; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni
abstract

In this brief, we investigate the bidirectional threshold voltage drift (VT) following negative-bias temperature instability (NBTI) stress in carbon-doped fully recessed AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Several stress conditions were applied at different: 1) gate biases (VGS,STR); 2) stress times (tSTR); and 3) temperatures (T). Both negative and positive VT (thermally activated with different activation energies, EA) were observed depending on the magnitude of VGS,STR. In accordance with the literature, observed VT < 0 V (EA ≈ 0.5 eV) under moderate stress is attributed to the emission of electrons from oxide and interface traps. Instead, VT > 0 V (EA ≈ 0.9 eV) under high stress is attributed to the increased negatively ionized acceptor trap density in the buffer associated with carbon doping.

2021 - Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing [Articolo su rivista]
Zanotti, Tommaso; Pavan, Paolo; Puglisi, Francesco Maria
abstract

2021 - On the Modeling of the Donor/Acceptor Compensation Ratio in Carbon‐Doped GaN to Univocally Reproduce Breakdown Voltage and Current Collapse in Lateral GaN Power HEMTs [Articolo su rivista]
Zagni, Nicolo'; Chini, Alessandro; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni
abstract

The intentional doping of lateral GaN power high electron mobility transistors (HEMTs) with carbon (C) impurities is a common technique to reduce buffer conductivity and increase breakdown voltage. Due to the introduction of trap levels in the GaN bandgap, it is well known that these impurities give rise to dispersion, leading to the so‐called “current collapse” as a collateral effect. Moreover, first‐principles calculations and experimental evidence point out that C introduces trap levels of both acceptor and donor types. Here, we report on the modeling of the donor/acceptor compensation ratio (CR), that is, the ratio between the density of donors and acceptors associated with C doping, to consistently and univocally reproduce experimental breakdown voltage (VBD) and current‐collapse magnitude (ΔICC). By means of calibrated numerical device simulations, we confirm that ΔICC is controlled by the effective trap concentration (i.e., the difference between the acceptor and donor densities), but we show that it is the total trap concentration (i.e., the sum of acceptor and donor densities) that determines VBD, such that a significant CR of at least 50% (depending on the technology) must be assumed to explain both phenomena quantitatively. The results presented in this work contribute to clarifying several previous reports, and are helpful to device engineers interested in modeling C‐doped lateral GaN power HEMTs.

2021 - Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories [Articolo su rivista]
Puglisi, F. M.; Zanotti, T.; Pavan, P.
abstract

In this paper, we revisit Boole's expansion theorem to propose a new synthesis method for implication logic circuits based on memristors. By rewriting the sum-of-products form of Boole's expansion theorem in terms that are best suited for the implication logic, we develop a generalized rule to derive the sequence of operations needed to realize any logic function written in the classical AND-OR form. The proposed method leverages on multi-input operation, minimizing both the number of steps required to compute a given Boolean function and the number of memristors involved. Moreover, it allows using well-established methods of logic circuit optimization like binary decision diagrams, Karnaugh maps, and heuristic algorithms, that are already implemented in commercial CAD software. The proposed method allows a fair comparison between the performance of CMOS and implication logic implementations of the same logic function under the same degree of optimization, and is shown to outperform existing approaches. Possible device-circuit co-design strategies to optimize circuit performance are finally discussed.

2021 - Performances and Trade-offs of Low-Bit Precision Neural Networks based on Resistive Memories [Relazione in Atti di Convegno]
Zanotti, T.; Pavan, P.; Puglisi, F. M.
abstract

In this work we devise and train a RRAM-based low-precision neural network with binary weights and 4-bits activations. Full-circuit simulations including the analog neuron peripheral circuitry are run in different conditions, including the effect of RRAM devices nonidealities, to evaluate the reliability and performance of the network when executing a classification task. Results show that the power-throughput trade-off during inference is governed by the neuron circuitry, and that the reset conditions can be tuned to simultaneously maximize energy efficiency and accuracy leading to improved network reliability. Accuracy losses are found to be dominated by the variability of the RRAMs in low resistive state (LRS), which suggests specific strategies for accuracy loss minimization. The network shows excellent performance in terms of accuracy, throughput, and energy efficiency, with robustness to RRAM non-idealities.

2021 - Reliability and Performance Analysis of Logic-in-Memory Based Binarized Neural Networks [Articolo su rivista]
Zanotti, T.; Puglisi, F. M.; Pavan, P.
abstract

Resistive Random access memory (RRAM) devices together with the material implication (IMPLY) logic are a promising computing scheme for realizing energy efficient reconfigurable computing hardware for edge computing applications. This approach has been recently shown to enable the in-memory implementation of Binarized Neural Networks. However, an accurate analysis of the performance achieved on a real classification task are still missing. In this work, we train and estimate the performance of an IMPLY-based implementation of a multilayer perceptron (MLP) BNN and highlight its main reliability challenges by using a physics-based RRAM compact model calibrated on three RRAM technologies from the literature. We then show how the smart IMPLY (SIMPLY) architecture solves the reliability issues of conventional IMPLY architectures and compare its performance with respect to conventional solutions considering different parallelization degree. The worst-case energy estimates for an inference task performed on the trained network, show that the SIMPLY implementation results in a >46 energy-delay-product (EDP) improvement with respect to a conventional low-power embedded system implementation.

2021 - STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing [Articolo su rivista]
De Rose, Raffaele; Zanotti, Tommaso; Maria Puglisi, Francesco; Crupi, Felice; Pavan, Paolo; Lanuzza, Marco
abstract

Spin-transfer torque magnetic tunnel junction (STT-MTJ) technology is an attractive solution for designing non-volatile Logic-in-Memory (LIM) architectures. This work explores a smart material implication (SIMPLY) LIM scheme based on nanoscale STT-MTJs. The SIMPLY architecture is benchmarked against the conventional material implication (IMPLY) logic. Obtained results prove that for similar performance the STT-MTJ based SIMPLY scheme ensures more reliable operation (i.e., lower error rate by more than three orders of magnitude) and an energy saving of -70% than its IMPLY counterpart, at the only cost of minimal area overhead.

2021 - Validating Photoplethysmography (PPG) data for driver drowsiness detection [Relazione in Atti di Convegno]
Amidei, A.; Fallica, P. G.; Conoci, S.; Pavan, P.
abstract

Drowsiness is one of the first casualty factors of car accidents. A large number of studies have been conducted to reduce the risk of car accidents and, many of them, are based on the detection of biological signals to determine driver drowsiness. In this way, several prototypes have been proposed but all of them are efficient in specific scenarios only. Photoplethysmography (PPG) is a non-invasive tool that allows monitoring heart activity, it is also used to evaluate driver drowsiness. This paper introduces a prototype based on PPG signals able to improve current systems in terms of evaluation time and results clearness. We performed a measurement campaign to compare experimental data with literature. The goal is to validate the prototype.

2021 - “Hole Redistribution” Model Explaining the Thermally Activated RON Stress/Recovery Transients in Carbon-Doped AlGaN/GaN Power MIS-HEMTs [Articolo su rivista]
Zagni, Nicolo'; Chini, Alessandro; Puglisi, Francesco Maria; Meneghini, Matteo; Meneghesso, Gaudenzio; Zanoni, Enrico; Pavan, Paolo; Verzellesi, Giovanni
abstract

RON degradation due to stress in GaN-based power devices is a critical issue that limits, among other effects, long-term stable operation. Here, by means of 2-D device simulations, we show that the RON increase and decrease during stress and recovery experiments in carbon-doped AlGaN/GaN power metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) can be explained with a model based on the emission, redistribution, and retrapping of holes within the carbon-doped buffer (“hole redistribution” in short). By comparing simulation results with front- and back-gating OFF-state stress experiments, we provide an explanation for the puzzling observation of both stress and recovery transients being thermally activated with the same activation energy of about 0.9 eV. This finds a straightforward justification in a model in which both RON degradation and recovery processes are limited by hole emission by dominant carbon-related acceptors that are energetically located at about 0.9 eV from the GaN valence band.

2020 - A memory window expression to evaluate the endurance of ferroelectric FETs [Articolo su rivista]
Zagni, Nicolo'; Pavan, Paolo; Ashraful Alam, Muhammad
abstract

The recent discovery of ferroelectricity in HfO2 has revived the interest into non-volatile memories based on ferroelectric transistors (FeFETs). The key advantages of these FeFETs include the low power consumption and the compatibility with the existing CMOS process. On the other hand, issues related mainly to endurance still represent a challenge to the development of the technology. In this Letter, we propose to exploit an analytical expression for the Memory Window (MW) as a simple yet effective characterization tool to evaluate the endurance of FeFETs. The MW is defined as the difference between threshold voltages occurring due to polarization switching. The analytical formulation of the MW allows one to quickly estimate the generated trap concentration as a function of number of writing cycles (or time) without recurring to numerical simulations. With the aid of the analytical model, we find that for typical program/erase pulse amplitudes and duration, endurance has a weak dependence on writing conditions. The characterization technique based on the MW would allow the systematic comparison of the performance and endurance of next-generation FeFETs.

2020 - Characterization and TCAD Modeling of Mixed-Mode Stress Induced by Impact Ionization in Scaled SiGe HBTs [Articolo su rivista]
Zagni, Nicolo; Puglisi, Francesco Maria; Verzellesi, Giovanni; Pavan, Paolo
abstract

We investigate the reliability of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) in 55-nm technology under mixed-mode stress. We perform electrical characterization and implement a TCAD model calibrated on the measurement data to describe the increased base current degradation at different collector-base voltages. We introduce a simple and self-consistent simulation methodology that links the observed degradation trend to interface traps generation at the emitter/base spacer oxide ascribed to hot holes generated by impact ionization (II) in the collector/base depletion region. This effectively circumvents the limitations of commercial TCAD tools that do not allow II to be the driving force of the degradation. The approach accounts for self-heating and electric fields distribution allowing to reproduce measurement data including the deviation from the power-law behavior.

2020 - Circuit Reliability Analysis of In-Memory Inference in Binarized Neural Networks [Relazione in Atti di Convegno]
Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
abstract

2020 - Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise [Relazione in Atti di Convegno]
Zanotti, T.; Puglisi, F. M.; Pavan, P.
abstract

The Logic-in-Memory paradigm is considered a promising solution for improving the energy efficiency and computing power of architectures aimed at low power and/or data-intensive applications. Among in-memory computing enabling technologies, emerging non-volatile memories (e.g., RRAMs) are promising as they offer BEOL integration and small feature size. Several studies have shown that IMPLY architectures based on RRAM devices and the material implication logic enable the efficient computation of logic operations using the RRAM device both as storing and computing element. However, RRAM devices non-idealities introduce important circuit reliability issues, that are frequently neglected, thus undermining the circuit functionality. In this work, we use a physics-based compact model calibrated on experimental data to simulate the IMPLY operation performed on a crossbar array including line parasitic effects and RRAM devices non-idealities. We then introduce a novel smart scheme, SIMPLY, and show the circuit reliability improvement.

2020 - Corrigendum to “Linearization of thermoacoustic loudspeakers by adaptive predistortion” [Sens. Actuators A: Phys. 297 (2019) 111551] (Sensors and Actuators: A. Physical (2019) 297, (S0924424719307903), (10.1016/j.sna.2019.111551)) [Articolo su rivista]
La Torraca, P.; Ricci, Y.; Bobinger, M.; Pavan, P.; Larcher, L.
abstract

The authors would like to add the following text as acknowledgement The authors would like to thank ASK industries S.P.A. for financial support and technical assistance. This work is supported by the Italian Ministry of Economic Development (MISE)'s FUND FOR THE SUSTAINABLE GROWTH (F.C.S) under grant agreement (CUP) B48I15000130008, project VASM (“Vehicle Active Sound Management”). The authors acknowledge the support of the Tiziano Nili (Project Leader) and Luca Cattani (Team Leader) The authors would like to apologise for any inconvenience caused.

2020 - Reconfigurable Smart In-Memory Computing Platform Supporting Logic and Binarized Neural Networks for Low-Power Edge Devices [Articolo su rivista]
Zanotti, T.; Puglisi, F. M.; Pavan, P.
abstract

Edge computing has been shown to be a promising solution that could relax the burden imposed onto the network infrastructure by the increasing amount of data produced by smart devices. However, reconfigurable ultra-low power computing architectures are needed. RRAM devices together with the material implication logic (IMPLY) are a promising solution for the development of low-power reconfigurable logic-in-memory (LiM) hardware. Nevertheless, traditional approaches suffer from several issues introduced by the circuit topology and device non-idealities. Recently, SIMPLY, a smart LiM architecture based on the IMPLY, has been proposed and shown to solve the common issues of traditional architectures. Here, we use a physics-based RRAM compact model calibrated on three RRAM technologies to further analyze the performance of SIMPLY in typical operating conditions, when the repeated execution of logic operation on the same group of devices is considered. The results show that, compared to the conventional IMPLY architecture, SIMPLY spares more than 40% of the high voltage pulses on average even when complex operations are considered (e.g., the 1-bit half adder). We also show how SIMPLY can implement the set of operations required for the implementation of Binarized Neural Networks (BNN) and benchmark its performance against other memristor-based BNN in-memory accelerator from the literature. The results suggest that our approach is more than two orders of magnitude efficient compared to the state of the art reconfigurable in-memory computing approach and could potentially reach the performance of specialized BNN analog hardware accelerators with appropriate device-circuit co-design strategies.

2020 - Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays [Articolo su rivista]
Zanotti, T.; Zambelli, C.; Puglisi, F. M.; Milo, V.; Perez, E.; Mahadevaiah, M. K.; Ossorio, O. G.; Wenger, C.; Pavan, P.; Olivo, P.; Ielmini, D.
abstract

Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25-μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.

2020 - Reliability-Aware Design Strategies for Stateful Logic-in-Memory Architectures [Articolo su rivista]
Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
abstract

2020 - Smart Logic-in-Memory Architecture For Ultra-Low Power Large Fan-In Operations [Relazione in Atti di Convegno]
Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
abstract

The need for processing the continuously growing amount of data that is produced every day is promoting research for the development of energy-efficient non-von Neumann computing architectures. Over the last decade, resistive RAM (RRAM) devices together with material implication logic (IMPLY) were proposed as a promising solution for the development of low-power logic-in-memory (LIM) circuits. Still, the high design complexity and the low reliability of these circuits are hindering their practical realization. It is only recently that a new smart IMPLY architecture, named SIMPLY, was proposed and shown to drastically improve circuit reliability and energy efficiency of IMPLY-based LIM circuits. In this work, we introduce a new smart operation, called sFALSE, enabled by the SIMPLY architecture, and verify its feasibility using a physics-based RRAM compact model calibrated on three different technologies. We highlight the significant advantage of the proposed solution vs. ordinary IMPLY architecture in terms of energy reduction, especially for large fan-in logic operations (e.g., n-bits NAND and EXOR).

2020 - Smart Logic-in-Memory Architecture for Low-Power non-von Neumann Computing [Articolo su rivista]
Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
abstract

Low-power smart devices are becoming pervasive in our world. Thus, relevant research efforts are directed to the development of innovative low power computing solutions that enable in-memory computations of logic-operations, thus avoiding the von Neumann bottleneck, i.e., the known showstopper of traditional computing architectures. Emerging non-volatile memory technologies, in particular Resistive Random Access memories, have been shown to be particularly suitable to implement logic-in-memory (LIM) circuits based on the material implication logic (IMPLY). However, RRAM devices nonidealities, logic state degradation, and a narrow design space limit the adoption of this logic scheme. In this work, we use a physics-based compact model to study an innovative smart IMPLY (SIMPLY) logic scheme which exploits the peripheral circuitry embedded in ordinary IMPLY architectures to solve the mentioned reliability issues, drastically reducing the energy consumption and setting clear design strategies. We then use SIMPLY to implement a 1-bit full adder and compare the results with other LIM solutions proposed in the literature.

2020 - Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-Of-The-Roadmap III-V MOSFETs [Articolo su rivista]
Zagni, Nicolò; Caruso, Enrico; Puglisi, Francesco Maria; Pavan, Paolo; Palestri, Pierpaolo; Verzellesi, Giovanni
abstract

Thanks to their superior transport properties, Indium Gallium Arsenide (InGaAs) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) constitute an alternative to conventional Silicon MOSFETs for digital applications at ultra-scaled nodes. The successful integration of this technology is challenged mainly by the high defect density in the gate oxide and at the interface with the semiconductor channel, which degrades the electrostatics and could limit the potential benefits over Si. In this work, we i) establish a systematic modeling approach to evaluate the performance degradation due to interface traps in terms of electrostatics and transport of InGaAs Dual-Gate Ultra-Thin Body (DG-UTB) FETs, and ii) investigate the effects of random interface-trap concentration as another roadblock to the scaling of the technology, due to statistical variability of the threshold voltage. Variability is assessed with a Technology CAD (TCAD) simulator calibrated against Multi-Subband Monte Carlo (MSMC) simulations. The modeling approach overcomes the TCAD limitations when dealing with ultra-thin channels (i.e., below 5 nm) without altering crucial geometrical parameters that would compromise the dependability of the variability analysis. Our results indicate that interface-trap fluctuation becomes comparable with the other variability sources dominating the total variability when shrinking the device dimensions, thus contrasting the trend of reduced variability with scaling. This in turn implies that interface and border traps may strongly limit the benefits of InGaAs over Silicon if not effectively reduced by gate process optimization.

2020 - The Role of Carbon Doping on Breakdown, Current Collapse and Dynamic On-Resistance Recovery in AlGaN/GaN High Electron Mobility Transistors on Semi‐Insulating SiC Substrates [Articolo su rivista]
Zagni, Nicolò; Chini, Alessandro; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni
abstract

In this work, the critical role of carbon doping in the electrical behavior of AlGaN/GaN High Electron Mobility Transistors (HEMTs) on semi-insulating SiC substrates is assessed by investigating the off-state three terminal breakdown, current collapse and dynamic on-resistance recovery at high drain-source voltages. Extensive device simulations of typical GaN HEMT structures are carried out and compared to experimental data from published, state-of-the-art technologies to: i) explain the slope of the breakdown voltage as a function of the gate-to-drain spacing lower than GaN critical electric field as a result of the non-uniform electrical field distribution in the gate-drain access region; ii) attribute the drain current collapse to trapping in deep acceptor states in the buffer associated with carbon doping; iii) interpret the partial dynamic on-resistance recovery after off-state stress at high drain-source voltages as a consequence of hole generation and trapping.

2020 - The effects of carbon on the bidirectional threshold voltage instabilities induced by negative gate bias stress in GaN MIS-HEMTs [Articolo su rivista]
Zagni, Nicolò; Chini, Alessandro; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni
abstract

In this paper, numerical device simulations are used to point out the possible contributions of carbon doping to the threshold voltage instabilities induced by negative gate bias stress in AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistors. It is suggested that carbon can have a role in both negative and positive threshold voltage shifts, as a result of (1) the changes in the total negative charge stored in the carbon-related acceptor traps in the GaN buffer, and (2) the attraction of carbon-related free holes to the device surface and their capture into interface traps or recombination with gate-injected electrons. For a proper device optimization of carbon-doped MIS-HEMTs, it is therefore important to take these mechanisms into account, in addition to those related to defects in the gate dielectric volume and interface which are conventionally held responsible for threshold voltage instabilities.

2020 - Trap Dynamics Model Explaining the RON Stress/Recovery Behavior in Carbon-Doped Power AlGaN/GaN MOS-HEMTs [Relazione in Atti di Convegno]
Zagni, Nicolo; Chini, Alessandro; Puglisi, Francesco Maria; Pavan, Paolo; Meneghini, Matteo; Meneghesso, Gaudenzio; Zanoni, Enrico; Verzellesi, Giovanni
abstract

In this paper, we present simulation results that reproduce stress and recovery experiments in Carbon-doped power GaN MOS-HEMTs and explain the associated R ON increase and decrease as the result of the emission, redistribution and re-trapping of holes within the Carbon-doped buffer. The proposed model can straightforwardly clarify the beneficial impact of the recently proposed p-type drain contact on R ON degradation as being a consequence of enhanced hole trapping and reduced negative trapped charge within the buffer during stress.

2019 - Advanced modeling and characterization techniques for innovative memory devices: The RRAM case [Capitolo/Saggio]
Puglisi, Francesco Maria; Padovani, Andrea; Pavan, Paolo; Larcher, Luca
abstract

2019 - An Ultra-Low Cost Triboelectric Flowmeter [Capitolo/Saggio]
Bertacchini, A.; Pavan, P.
abstract

In this paper, we present an ultra-low cost flowmeter suitable for both gases and fluids. Differently from other flowmeters presented in the literature, the prototype is based on the triboelectric effect. The realized device is extremely low cost because it uses commercial silicone as triboelectric material. The comparison between experimental measurements and output data of a commercial flowmeter, used as reference, demonstrates the effectiveness of the proposed solution in both constant and variable flow conditions. Moreover, thanks to its reconfigurable architecture, the realized device can be used for both redundant measurements and triboelectric energy harvesting purposes.

2019 - Boron Vacancies Causing Breakdown in 2D Layered Hexagonal Boron Nitride Dielectrics [Articolo su rivista]
Ranjan, A.; Raghavan, N.; Puglisi, F. M.; Mei, S.; Padovani, A.; Larcher, L.; Shubhakar, K.; Pavan, P.; Bosman, M.; Zhang, X. X.; O'Shea, S. J.; Pey, K. L.
abstract

Dielectric breakdown in 2D insulating films for future logic device technology is not well understood yet, in contrast to the extensive insight we have in the breakdown of bulk dielectric films, such as HfO2 and SiO2. In this letter, we investigate the stochastic nature of breakdown (BD) in hexagonal boron nitride (h-BN) films using ramp voltage stress and examine the BD trends as a function of stress polarity, area, and temperature. We present evidence that points to a non-Weibull distribution for h-BN BD and use the multi-scale physics-based simulations to extract the energetics of the defects that are precursors to BD, which happens to be boron vacancies.

2019 - Circuit reliability of low-power rram-based logic-in-memory architectures [Relazione in Atti di Convegno]
Zanotti, T.; Puglisi, F. M.; Pavan, P.
abstract

Logic circuits based on Resistive RAM (RRAM) devices and the material implication logic (IMPLY) are promising solutions for low-power logic-in-memory (LiM) architectures. Still, their diffusion is limited by their high design complexity resulting from device and circuit non-idealities. These non-idealities are usually overlooked in the design phase when using simplified RRAM models, thus leading to unreliable designs. In this work, we derive correct design strategies for reliability of RRAM-based LiM circuits and quantitatively evaluate circuit performances using a physics-based compact model.

2019 - Effects of mole fraction variations and scaling on total variability in InGaAs MOSFETs [Articolo su rivista]
Zagni, N.; Puglisi, F. M.; Pavan, P.; Verzellesi, G.
abstract

Variability is one of the major roadblocks for III-V semiconductors in nanoscale devices, according to the recent International Roadmap for Devices and Systems (IRDS). A particular concern is the detrimental effect of variability of threshold voltage due to channel compositional variations. In this paper, we investigate the impact of this variability source and the effects of scaling on the performance of Dual-Gate-Ultra-Thin-Body (DG-UTB) In0.53Ga0.47As MOSFETs. We model mole fraction variations in terms of the Indium content by taking into account the spatial inhomogeneity of the channel and the corresponding bandgap variations, analyzing the effects on threshold voltage variability. We thus define a variability source, i.e., Band Gap Fluctuation (BGF), and we compare the associated variability with the ones from other important sources, namely, Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate-Line Edge Roughness (B-LER and G-LER). We then define three corner cases for mole fraction variations to determine worst-case variability. Finally, the impact of scaling on variability is assessed by comparing results for two technology nodes on the linear and saturation threshold voltage, V-T,V-lin,V- V-T,V-sat, on-current, I-ON, leakage current, I-OFF, and linear and saturation sub-threshold slope, SS. We find that although scaling has no impact on BGF-induced V-T variability, it increases the total V-T, lin variability as well as that for I-ON and I-OFF.

2019 - Insights into the off-state breakdown mechanisms in power GaN HEMTs [Articolo su rivista]
Zagni, Nicolo'; Puglisi, F. M.; Pavan, P.; Chini, A.; Verzellesi, G.
abstract

We analyze the off-state, three-terminal, lateral breakdown in AlGaN/GaN HEMTs for power switching applications by comparing two-dimensional numerical device simulations with experimental data from device structures with different gate-to-drain spacing and with either undoped or Carbon-doped GaN buffer layer. Our simulations reproduce the different breakdown-voltage dependence on the gate-drain-spacing exhibited by the two types of device and attribute the breakdown to: i) a combination of gate electron injection and source-drain punch-through in the undoped HEMTs; and ii) avalanche generation triggered by gate electron injection in the C-doped HEMTs.

2019 - Linearization of thermoacoustic loudspeakers by adaptive predistortion [Articolo su rivista]
La Torraca, P.; Ricci, Y.; Bobinger, M.; Pavan, P.; Larcher, L.
abstract

In this work we present a novel driving technique for thermoacoustic (TA) loudspeakers. The proposed technique allows linearizing the pressure response of TA loudspeakers while reducing the average power dissipation on the device, and thus its working temperature. This is achieved exploiting an adaptive predistortion algorithm, implemented through digital signal processing. The controlled TA loudspeakers show exceptionally low values of total harmonic distortion and intermodulation distortion in their pressure response, exceeding the performance of previously proposed techniques, and a significantly reduced working temperature.

2019 - METODO DI LETTURA PER CIRCUITI DEL TIPO LOGIC-IN-MEMORY E RELATIVA ARCHITETTURA CIRCUITALE [Brevetto]
Puglisi, Francesco Maria; Pavan, Paolo; Zanotti, Tommaso
abstract

2019 - Mixed-Mode Stress in Silicon-Germanium Heterostructure Bipolar Transistors: Insights from Experiments and Simulations [Articolo su rivista]
Puglisi, F. M.; Larcher, L.; Pavan, P.
abstract

Recently, a wide class of market segments (e.g., health, material science, security, and communications) is tackled by circuits fabricated in BiCMOS technology, integrating silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and passives. Currently, the reliability of SiGe HBT devices is a major concern, and much attention is given to self-heating (SH), that limits device performance and regulates their degradation during stress. Moreover, its relevance is supposed to increase with device scaling. In this paper, we explore the reliability issues of SiGe HBTs by combining dedicated experiments and TCAD simulations. We develop and calibrate a TCAD model that is then used to investigate SH effects in both operating and stress conditions. Results show the important role played by the back-end-of-line (BEOL) and by the substrate thermal resistance in dissipating the heat generated by impact ionization. The location at which defects are generated during stress and the microscopic properties of the defects are determined experimentally by means of dedicated noise measurements. Including defects in the TCAD model allows reproducing the degradation observed in stress experiments. Simulations of the SH effects on a stressed device in measurement conditions revealed the presence of a hole hot spot that suggests a possible physical mechanism involved in the degradation slowdown at long stress times reported in the literature.

2019 - Printed Technology Solutions for Audio Transducers [Relazione in Atti di Convegno]
Torraca, P. L.; Ricci, Y.; Albrecht, A.; Bobinger, M.; Pavan, P.; Cattani, L.; Becherer, M.; Lugli, P.; Larcher, L.
abstract

We propose novel printed technology solutions for the fabrication of electro-acoustic audio transducers. Flexible, transparent thermoacoustic (TA) loudspeakers are fabricated using spray coating of silver nanowires (AgNWs) on a 75 μ m thin polyimide substrate. The fabricated devices show interesting optical and electric properties for integration in audio systems. The thermal and the acoustic characterizations shows very good agreement with the models proposed in literature. The proposed technology achieves up to 40 dB SPL at 1m distance, retaining its properties even under large substrate deformations.

2019 - Recommended Methods to Study Resistive Switching Devices [Articolo su rivista]
Lanza, Mario; Wong, H. -S. Philip; Pop, Eric; Ielmini, Daniele; Strukov, Dimitri; Regan, Brian C.; Larcher, Luca; Villena, Marco A.; Yang, J. Joshua; Goux, Ludovic; Belmonte, Attilio; Yang, Yuchao; Puglisi, Francesco M.; Kang, Jinfeng; Magyari-Köpe, Blanka; Yalon, Eilam; Kenyon, Anthony; Buckwell, Mark; Mehonic, Adnan; Shluger, Alexander; Li, Haitong; Hou, Tuo-Hung; Hudec, Boris; Akinwande, Deji; Ge, Ruijing; Ambrogio, Stefano; Roldan, Juan B.; Miranda Castellano, Enrique Alberto; Suñe, Jordi; Pey, Kin Leong; Wu, Xing; Raghavan, Nagarajan; Wu, Ernest; Lu, Wei D.; Navarro, Gabriele; Zhang, Weidong; Wu, Huaqiang; Li, Runwei; Holleitner, Alexander; Wurstbauer, Ursula; Lemme, Max C.; Liu, Ming; Long, Shibing; Liu, Qi; Lv, Hangbing; Padovani, Andrea; Pavan, Paolo; Valov, Ilia; Jing, Xu; Han, Tingting; Zhu, Kaichen; Chen, Shaochuan; Hui, Fei; Shi, Yuanyuan
abstract

Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, with electronic nonvolatile memories being those that have received the most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology.

2019 - SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model [Relazione in Atti di Convegno]
Puglisi, F. M.; Zanotti, T.; Pavan, P.
abstract

In this work, we introduce a new RRAM-based Smart IMPLY (SIMPLY) logic scheme with unique benefits for low-power systems and verify its feasibility and advantages by means of circuit simulations allowing appropriate device/circuit requirements co-design. Differently from previous works, we use a physics-based compact model of RRAM devices able to reproduce both the ultrafast AC and the DC behavior, accounting for the intrinsic variability of the resistive states, the occurrence of Random Telegraph Noise, and the logic state degradation. The proposed scheme strongly alleviates the issue of logic state degradation, breaks the trade-off between the choice of VSET and VCOND, and allows saving energy up to a factor of ~230 requiring minimum area overhead.

2019 - Two-dimensional MoS2 negative capacitor transistors for enhanced (super-Nernstian) signal-to-noise performance of next-generation nano biosensors [Articolo su rivista]
Zagni, N.; Pavan, P.; Alam, M. A.
abstract

The detection of biomolecules by a Field Effect Transistor-based biosensor (BioFET) is dictated by the sensor's intrinsic Signal-to-Noise Ratio (SNR). The detection limit of a traditional BioFET is fundamentally limited by biomolecule diffusion, charge screening, linear charge to surface-potential transduction, and Flicker noise. In this letter, we show that the recently introduced class of transistors called negative capacitor field effect transistors offers nonlinear charge transduction and suppression of Flicker noise to dramatically improve the SNR over classical Boltzmann sensors. We quantify the SNR improvement (approximately two orders of magnitude higher than a classical Si-nanowire biosensor) by interpreting the experimental results associated with the signal and noise characteristics of 2D MoS2-based transistors. The proposed Negative Capacitor BioFET (NC-BioFET) will motivate experimentalists to combine two well-established technologies to achieve high SNR (and to improve the detection limit), fundamentally unachievable by any other sensor technology.

2019 - Understanding current instabilities in conductive atomic force microscopy [Articolo su rivista]
Jiang, Lanlan; Weber, Jonas; Puglisi, Francesco Maria; Pavan, Paolo; Larcher, Luca; Frammelsberger, Werner; Benstetter, Guenther; Lanza, Mario
abstract

Conductive atomic force microscopy (CAFM) is one of the most powerful techniques in studying the electrical properties of various materials at the nanoscale. However, understanding current fluctuations within one study (due to degradation of the probe tips) and from one study to another (due to the use of probe tips with different characteristics), are still two major problems that may drive CAFM researchers to extract wrong conclusions. In this manuscript, these two issues are statistically analyzed by collecting experimental CAFM data and processing them using two different computational models. Our study indicates that: (i) before their complete degradation, CAFM tips show a stable state with degraded conductance, which is difficult to detect and it requires CAFM tip conductivity characterization before and after the CAFM experiments; and (ii) CAFM tips with low spring constants may unavoidably lead to the presence of a ~1.2 nm thick water film at the tip/sample junction, even if the maximum contact force allowed by the setup is applied. These two phenomena can easily drive CAFM users to overestimate the properties of the samples under test (e.g., oxide thickness). Our study can help researchers to better understand the current shifts that were observed during their CAFM experiments, as well as which probe tip to use and how it degrades. Ultimately, this work may contribute to enhancing the reliability of CAFM investigations.

2019 - Unimore Resistive Random Access Memory (RRAM) Verilog-A Model 1.0.0 [Software]
Puglisi, Francesco Maria; Zanotti, Tommaso; Pavan, Paolo
abstract

The Unimore RRAM Verilog-A model is a physics-based compact model of bipolar RRAM which includes cycle-to-cycle variability, thermal effects, self-heating, and multilevel Random Telegraph Noise (RTN). The model considers both the quasi-ohmic charge transport along the conductive filament and the trap-assisted tunneling transport in the dielectric barrier. The reset/set operations dynamics is modeled with differential equations considering the field-driven oxygen ions drift and recombination during reset (i.e., barrier growth), and the field accelerated bond breakage during set (i.e., barrier collapse). The temperature dynamics is, likewise, modeled with differential equations that enable accurate predictions also when using very short pulses. Thus, the model enables the advanced design of circuits for many applications such as Memory, Neuromorphic Circuits, RRAM-based Neural Networks, Logic-In-Memory Systems, Physical Unclonable Functions, True Random Number Generators and others.

2018 - Characterization and Modeling of Low-Cost Contact-Mode Triboelectric Devices for Energy Harvesting [Relazione in Atti di Convegno]
Bertacchini, A.; Lasagni, M.; Sereni, G.; Larcher, L.; Pavan, P.
abstract

In this paper we investigate the effect of the contact force in Contact-Mode TriboElectric Devices (CM-TED). In this kind of devices, the generated output voltage and the electrical energy harvested from mechanical impacts depend on the contact force. The number of impacts and the contact force influences also the surface charge density of the triboelectric layers of CM-TED. This is confirmed by the measurements carried out on the low-cost CM-TED prototypes we realized using commercial silicone as triboelectric material. The effect of the impact force has been included into a device model suitable for both dielectric-to-dielectric and contact-to-dielectric triboelectric devices. The model predicts the output voltage and power at given conditions and it can be used to design ultra-low cost triboelectric energy harvesters. The realized prototypes provide up to 5.5µW when subjected to repetitive impacts with a contact force of 65N.

2018 - Energy-efficient logic-in-memory I-bit full adder enabled by a physics-based RRAM compact model [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pacchioni, Lorenzo; Zagni, Nicolo; Pavan, Paolo
abstract

In this work, we explore the RRAM-based IMPLY logic by means of circuit simulations. Differently from previous works, we use a physics-based compact model of RRAM devices able to reproduce both the AC and the DC behavior, accounting for the intrinsic variability of the resistive states and the logic state degradation. A new implementation of a 1-bit full adder with unique properties for low-power circuits is proposed, and its performance in terms of energy consumption and execution time is evaluated by simulations. Results are compared against recent experiments, demonstrating a good agreement and indicating the direction for further improvement.

2018 - Extracting Atomic Defect Properties From Leakage Current Temperature Dependence [Articolo su rivista]
Larcher, Luca; Padovani, Andrea; Puglisi, Francesco Maria; Pavan, Paolo
abstract

In modern electronic devices, a variety of novel materials have been introduced such as transition metal oxides, chalcogenides, ferroelectric, and magnetic materials. The electrical response of such materials, used also as active layers, is strongly affected by atomic defects, which affect device performances, variability, and reliability. Extracting the defect properties (i.e., density, energy, and atomic nature) is, thus, crucial to both engineer the performances of electron devices and correctly project their scaling potential and reliability. In this paper, we propose a simple method to extract the atomic properties of defects from the thermal activation energy of the leakage current using a charge trapping relaxation model.

2018 - High Efficiency Thermoacoustic Loudspeaker Made with a Silica Aerogel Substrate [Articolo su rivista]
La Torraca, P.; Bobinger, M.; Pavan, P.; Becherer, M.; Zhao, S.; Koebel, M.; Cattani, L.; Lugli, P.; Larcher, L.
abstract

The extremely low thermal effusivity of the silica aerogel is exploited to develop a high efficiency thermoacoustic (TA) loudspeaker with solid substrate. The deposition of the electrically conductive, low heat capacity active film on the silica aerogel surface is achieved with both the spray coating of silver nanowires and the sputter coating of gold films. The uniform spray coating of the hydrophobic silica aerogel is enabled by a low pressure plasma treatment, which however impairs its robustness. The spray-coated samples prove to be fragile when subjected to elevated temperatures and thus not suitable for TA applications. Sputter coating, not requiring any treatment of the aerogel surface, allows the fabrication of working TA loudspeaker samples with a 100 nm gold active film. The electroacoustic response of the gold-sputtered silica aerogel TA loudspeaker is characterized at different input power levels. The experimental results are compared with those present in literature, showing an improved efficiency with respect to the other TA loudspeakers with solid substrate.

2018 - On the frequency response of nanostructured thermoacoustic loudspeakers [Articolo su rivista]
La Torraca, P.; Bobinger, M.; Servadio, M.; Pavan, P.; Becherer, M.; Lugli, P.; Larcher, L.
abstract

In this work, we investigate the thermal and acoustic frequency responses of nanostructured thermoacoustic loudspeakers. An opposite frequency dependence of thermal and acoustic responses was found independently of the device substrate (Kapton and glass) and the nanometric active film (silver nanowires and nm-thick metal films). The experimental results are interpreted with the support of a comprehensive electro-thermo-acoustic model, allowing for the separation of the purely thermal effects from the proper thermoacoustic (TA) transduction. The thermal interactions causing the reported opposite trends are understood, providing useful insights for the further development of the TA loudspeaker technology.

2018 - On the impact of channel compositional variations on total threshold voltage variability in nanoscale InGaAs MOSFETs [Relazione in Atti di Convegno]
Zagni, Nicolo; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni
abstract

In this paper we present an analysis of the impact of channel compositional variations on the total threshold voltage variability in nanoscale III-V MOSFETs. The analysis is carried out on a template Dual-Gate Ultra-Thin Body (DG-UTB) MOSFET through TCAD simulations in Sentaurus by Synopsys. The Impedance Field Method (IFM) is employed to evaluate statistical variability for five different sources: Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate-Line Edge Roughness (B-LER and G-LER) and Band Gap Fluctuation (BGF). BGF arises due to the compositional variations of Indium in the compound semiconductor composing the channel, namely InGaAs. Our analysis shows that, by appropriately modeling band gap fluctuations, it is possible to identify a worst-case total relative Vt variability for different amounts of Indium mole fraction variations, providing technologists with an important reference. Side-effects of channel compositional variations on other variability sources are evaluated as well, and are found to have a non-negligible impact on B-LER only.

2018 - Random Telegraph Noise in Resistive Random Access Memories: Compact Modeling and Advanced Circuit Design [Articolo su rivista]
Puglisi, Francesco Maria; Zagni, Nicolo; Larcher, Luca; Pavan, Paolo
abstract

In this paper, we report about the derivation of a physics-based compact model of random telegraph noise (RTN) in HfO2-based resistive random access memory (RRAM) devices. Starting from the physics of charge transport, which is different in the high resistive states and low resistive states, we explore the mechanisms responsible for RTN exploiting a hybrid approach, based on self-consistent physics simulations and geometrical simplifications. Then, we develop a simple yet effective physics-based compact model of RTN valid in both states, which can be steadily integrated in state-of-the-art RRAM compact models. The RTN compact model predictions are validated by comparison with both a large experimental data set obtained by measuring RRAM devices in different conditions, and data reported in the literature. In addition, we show how the model enables advanced circuit simulations by exploring three different circuits for memory, security, and logic applications.

2018 - Random telegraph noise in 2D hexagonal boron nitride dielectric films [Articolo su rivista]
Ranjan, A.; Puglisi, F. M.; Raghavan, N.; O'Shea, S. J.; Shubhakar, K.; Pavan, P.; Padovani, A.; Larcher, L.; Pey, K. L.
abstract

This study reports the observation of low frequency random telegraph noise (RTN) in a 2D layered hexagonal boron nitride dielectric film in the pre- and post-soft breakdown phases using conductive atomic force microscopy as a nanoscale spectroscopy tool. The RTN traces of the virgin and electrically stressed dielectric (after percolation breakdown) were compared, and the signal features were statistically analyzed using the Factorial Hidden Markov Model technique. We observe a combination of both two-level and multi-level RTN signals in h-BN, akin to the trends commonly observed for bulk oxides such as SiO2 and HfO2. Experimental evidence suggests frequent occurrence of unstable and anomalous RTN traces in 2D dielectrics which makes extraction of defect energetics challenging.

2018 - Self-Heating Effect in Silicon-Germanium Heterostructure Bipolar Transistors in Stress and Operating Conditions [Relazione in Atti di Convegno]
Puglisi, Fm; Ghillini, M; Larcher, L; Pavan, P
abstract

In recent times many systems in a wide range of application fields (e.g., health, material science, security, and communications) exploit the mm-and sub-mm-wave spectrum, which dramatically sped up the growth of the BiCMOS technology integrating silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) and passives. Today, the reliability of such devices is of primary concern, and particular attention is given to the device self-heating (SH), the importance of which is supposed to increase with the device scaling. In this work we develop a TCAD model for SiGe HBT devices that is used to investigate the SH effects in SiGe HBTs both in operating and stress conditions. We underline the different role played by impact ionization and carriers' and lattice heating on the device degradation. Results show the important role played by the back end-of-line (BEOL) and by the substrate thermal resistance in dissipating the heat generated by impact ionization and hot carriers. Simulations of the SH effects in stress conditions excluded annealing as the possible reason for the degradation dynamics reported in the literature, while simulations of stressed devices in measurement conditions revealed the presence of a hole hot spot that suggests a possible physical mechanism involved in the degradation slowdown at long stress times reported in the literature.

2017 - A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Zagni, Nicolo'; Larcher, Luca; Pavan, Paolo
abstract

In this work, we propose for the first time a Verilog-A physics-based compact model of Random Telegraph Noise (RTN) in Resistive Random Access Memory (RRAM) devices. Starting from the physics of the RTN mechanism in both high (HRS) and low (LRS) resistive states, and combining experimental data with physics-based simulations, we develop and validate a complete compact model of RTN in RRAM devices. The model accounts for the intrinsic randomness in the number of defects contributing to the RTN and their properties. Moreover, it can be readily integrated in existing RRAM device compact models, extending their capabilities. The model is implemented in Verilog-A, and its effectiveness is demonstrated by using it to design the building block of a Truly-Random Number Generator circuit exploiting the RTN randomness as an entropy source.

2017 - Combined variability/sensitivity analysis in III-V and silicon FETs for future technological nodes [Relazione in Atti di Convegno]
Zagni, Nicolo'; Puglisi, Francesco Maria; Verzellesi, Giovanni; Pavan, Paolo
abstract

In this paper, we present a combined analysis of variability and sensitivity effects on electrical characteristics of In0.53Ga0.47As and Si ultra-scaled devices with LG= 15 nm. Two different structures, namely Dual-Gate and FinFET, are analyzed for both channel materials. Variability sources considered in this work are Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body-and Gate-Line Edge Roughness (LER). Sensitivity is assessed by varying process parameters, namely gate length, channel thickness, oxide thickness, and channel doping. Results show that variability in lnGaAs is dominated by both WFF and Body-LER, whereas WFF only dominates in Si devices. Moreover, control over gate length and channel thickness in In0.53Ga0.47As technology is fundamental in order to keep variability under reasonable values, with FinFET showing slightly better results than Dual-Gate structure. Variability is a major challenge for the industrial introduction of In0.53Ga0.47As, which could limit the alleged superior performance of In0.53Ga0.47As over Si.

2017 - Editorial EIC [Articolo su rivista]
Nathan, A.; Pavan, P.; Zetterling, C. -M.
abstract

2017 - Localized characterization of charge transport and random telegraph noise at the nanoscale in HfO2 films combining scanning tunneling microscopy and multi-scale simulations [Articolo su rivista]
Thamankar, R.; Puglisi, Francesco Maria; Ranjan, A.; Raghavan, N.; Shubhakar, K.; Molina, J.; Larcher, Luca; Padovani, Andrea; Pavan, Paolo; O'Shea, S. J.; Pey, K. L.
abstract

Charge transport and Random Telegraph Noise (RTN) are measured successfully at the nanoscale on a thin polycrystalline HfO2 film using room temperature Scanning Tunneling Microscopy (STM). STM is used to scan the surface of the sample with the aim of identifying grains and grain boundaries, which show different charge transport characteristics. The defects responsible for charge transport in grains and grain boundaries are identified as positively charged oxygen vacancies by matching the localized I-V curves measured at the nanoscale with the predictions of physics-based multi-scale simulations. The estimated defect densities at grains and grain boundaries agree with earlier reports in the literature. Furthermore, the current-time traces acquired by STM at fixed bias voltages on grains show characteristic RTN fluctuations. The high spatial resolution of the STM-based RTN measurement allows us to detect fluctuations related to individual defects that typically cannot be resolved by the conventional device-level probe station measurement. The same physical framework employed to reproduce the I-V conduction characteristics at the grains also successfully simulates the RTN detected at the nanoscale. We confirm that charge trapping at defects not directly involved in charge transport can induce significant current fluctuations through Coulombic interactions with other defects in the proximity that support charge transport.

2017 - Modelling nanoscale n-MOSFETs with III-V compound semiconductor channels: From advanced models for band structures, electrostatics and transport to TCAD [Relazione in Atti di Convegno]
Caruso, E.; Carapezzi, S.; Visciarelli, M.; Gnani, E.; Zagni, N.; Pavan, P.; Palestri, P.; Esseni, D.; Gnudi, A.; Reggiani, S.; Puglisi, F. M.; Verzellesi, G.; Selmi, L
abstract

We review a few state of the art solutions and recent developments to model short channel III-V compound semiconductor n-MOSFETs based on full quantum transport, semiclassical multi-valley / multi-subband transport and TCAD models. The pros and cons of each, and the insights they can deliver, are illustrated with examples from recent technology developments and literature. Areas where improvements and implementations at TCAD level are most necessary are highlighted as well.

2017 - Multiscale modeling of defect-related phenomena in high-k based logic and memory devices [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Puglisi, Francesco Maria; Pavan, Paolo
abstract

We present a multiscale modeling platform that exploits ab-initio calculation results and a material-related description of the most relevant defect-related phenomena in dielectrics (charge trapping and transport, degradation and atomic species motion) to interpret the reliability and electrical characteristics of logic and memory devices. The model is used to identify and characterize the dielectric defects responsible for the charge transport and degradation in SiOx/high-k (HK) bi-layer logic devices and to investigate the kinetics of forming and switching operations of Hf-based RRAM memories. Simulation results provide a deep and quantitative understanding of the factors controlling device operation and reliability. The proposed multiscale modeling platform represents a powerful tool for investigating material properties and optimizing device performances and reliability.

2017 - Physical modeling and characterization of thermo-acoustic loudspeakers made of silver nano-wire films [Articolo su rivista]
La Torraca, P.; Bobinger, M.; Pavan, Paolo; Seeber, B.; Lugli, P.; Larcher, L.
abstract

Recent developments of ultra-low heat capacity nanostructured materials revived the interest in the thermo-acoustic (TA) loudspeaker technology, which shows important advantages compared to the classical dynamic loudspeakers as they feature a lower cost and weight, flexibility, conformability to the surface of various shapes, and transparency. The development of the TA loudspeaker technology requires accurate physical models connecting the material properties to the thermal and acoustic speaker's performance. We present here a combined theoretical and experimental analysis of TA loudspeakers, where the electro-thermal and the thermo-acoustic transductions are handled separately, thus allowing an in-depth description of both the pressure and temperature dynamics. The electro-thermal transduction is analyzed by accounting for all the heat flow processes taking place between the TA loudspeaker and the surrounding environment, with focus on their frequency dependence. The thermo-acoustic conversion is studied by solving the coupled thermo-acoustic equations, derived from the Navier-Stokes equations, and by exploiting the Huygens-Fresnel principle to decompose the TA loudspeaker surface into a dense set of TA point sources. A general formulation of the 3D pressure field is derived summing up the TA point source contributions via a Rayleigh integral. The model is validated against temperature and sound pressure level measured on the TA loudspeaker sample made of a Silver Nanowire random network deposited on a polyimide substrate. A good agreement is found between measurements and simulations, demonstrating that the model is capable of connecting material properties to the thermo-acoustic performance of the device, thus providing a valuable tool for the design and optimization of TA loudspeakers.

2017 - Random dopant fluctuation variability in scaled InGaAs dual-gate ultra-thin body MOSFETs: source and drain doping effect [Relazione in Atti di Convegno]
Zagni, Nicolo; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni
abstract

In this paper, we present simulation results on statistical variability of threshold voltage and the respective sensitivity to process variations in Dual Gate Ultra-Thin Body (DG-UTB) InGaAs nMOSFETs at two technological nodes (with physical gate length Lg = 15 nm and Lg = 10.4 nm). Particularly, we focus on the effect of Random Dopant Fluctuations (RDF) in both the channel and the source/drain regions. While the effect of other variability sources (i.e., workfunction fluctuation, WFF, and line edge roughness, LER) can be controlled by existing technological strategies, RDF can become significant due to the 'source-starvation' effect. From our analysis, we find in fact that RDF is strongly dependent on source/drain doping, while the effect due to channel doping variation is marginal. Moreover, results indicate the possibility of achieving lower RDF variability effects at very high source/ drain doping levels that are beyond the reach of current process technology. Hence, RDF can potentially become the limiting factor to the overall variability in ultra-scaled InGaAs devices due to the difficulties in achieving very high source/drain doping.

2017 - Random telegraph noise: Measurement, data analysis, and interpretation [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

Abstract: In this paper, we delve into one of the most relevant defects-related phenomena causing failures in the operation of modern nanoscale electron devices, namely Random Telegraph Noise (RTN). Due to its detrimental impact on devices and circuits performances, RTN mechanism must be thoroughly understood, which requires establishing a self-consistent framework encompassing automated measurement techniques, data analysis algorithms, and physics-based modeling. This platform is not only required to understand the physics of RTN-related failures, but also to enable RTN analysis as a tool to investigate device reliability. Starting from the analysis of RTN signal statistical properties, we propose a set of guidelines to perform correct RTN measurements and data analysis, in order to get reliable results that are needed for an unbiased physical interpretation. This is achieved by combining automated experiments with sophisticated data analysis, consistency check, and comprehensive physics-based simulations. RTN analysis is then applied to two different devices for logic and memory applications, respectively: FinFETs and RRAMs. Particularly, the analysis of the statistical properties of RTN simultaneously measured on the drain and on the gate current of FinFETs allows understanding the details of the defects generation during stress. The analysis of RTN measured during the read operation in RRAM devices allows understanding the physical origin of RTN in these devices and identifying the defects species involved in this phenomenon.

2017 - Scaling perspective and reliability of conductive filament formation in ultra-scaled HfO2 Resistive Random Access Memory [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Celano, Umberto; Padovani, Andrea; Vandervorst, Wilfried; Larcher, Luca; Pavan, Paolo
abstract

In this paper we report about the scaling perspective of ultra-scaled HfO2 Resistive Random Access Memory devices. Due to filamentary conduction, the scalability of these devices is considered to be ultimately limited by the size of the conductive filament. However, even though the precise size and shape of the filament is not fully elucidated, it is widely accepted that its size is mainly controlled by the current compliance. In turn, the latter sets the operating current level of the cell. The reduction of the current level is nevertheless accompanied by performance instabilities, which are the main reliability threat for low-current operations. The resulting tradeoff raises concerns about the scalability potential of RRAM devices. In this work, we combine device-level measurements, Conductive Atomic-Force Microscopy (C-AFM), and physics-based simulations of HfO2 RRAM devices to elucidate the reason for these instabilities. Results clarify the scaling perspectives of ultra-low cell size (< 10×10 nm2) RRAMs and their reliability.

2017 - The impact of interface and border traps on current–voltage, capacitance–voltage, and split‐CV mobility measurements in InGaAs MOSFETs [Articolo su rivista]
Pavan, Paolo; Zagni, Nicolo'; Puglisi, Francesco Maria; Alian, Alireza; Thean, Aaron Voon Yew; Collaert, Nadine; Verzellesi, Giovanni
abstract

In this article, we present coupled experimental/simulated results about the influence of interface and border traps on the electrical characteristics and split-CV mobility extraction in InGaAs MOSFETs. These results show that border traps limit the maximum drain current under on-state conditions, induce a hysteresis in the quasi-static transfer characteristics, as well as affect CV measurements, inducing an increase in the accumulation capacitance even at high frequencies where trap effects are commonly assumed to be negligible. Hysteresis in the transfer characteristics can be used as a sensitive monitor of border traps, as suggested by a sensitivity analysis where either the energetic or the spatial distribution of border traps are varied. Finally, we show that mobility extraction by means of the split-CV method is affected by appreciable errors related to the spurious contributions of interface and border traps to the total gate charge, ultimately resulting in significant channel mobility underestimation. In very narrow channel devices, channel electron spilling over the InP buffer layer can also contribute to mobility measurement inaccuracy.

2017 - Threshold Voltage Statistical Variability and Its Sensitivity to Critical Geometrical Parameters in Ultrascaled InGaAs and Silicon FETs [Articolo su rivista]
Zagni, Nicolo'; Puglisi, Francesco Maria; Verzellesi, Giovanni; Pavan, Paolo
abstract

We investigate the statistical variability of the threshold voltage and its sensitivity to critical geometrical parameters in ultrascaled In0.53Ga0.47As and Si MOSFETs by means of 3-D quantum-corrected drift-diffusion simulations. Dual-gate ultrathin-body and FinFET device structures are analyzed for both channel materials. To assess the variability and sensitivity effects also from the scaling perspective, we consider devices belonging to two technological nodes with gate lengths 15 and 10.4 nm, designed according to International Technology Roadmap for Semiconductors (ITRS) specifications. Variability sources included in our analysis are random-dopant fluctuation, work-function fluctuation (WFF), as well as body- and gate-line-edge roughness (LER). Sensitivity to critical geometrical parameters is assessed by varying gate length, channel thickness, and oxide thickness. Results point out the major detrimental effect of WFF and Body-LER for InGaAs FETs, whereas WFF dominates in Si counterparts. Moreover, the sensitivity analysis shows that control over gate length and channel thickness in the InGaAs technology is fundamental in order to keep variability within tolerable values. Scaling of the InGaAs technology highlights the importance of abiding to ITRS projections regarding LER control improvement. Furthermore, a tight channel thickness control is required in ultrascaled devices due to the large sensitivity of the threshold voltage to the channel thickness combined with increased variability.

2017 - Variability and sensitivity to process parameters variations in InGaAs Dual-Gate Ultra-Thin Body MOSFETS: A scaling perspective [Relazione in Atti di Convegno]
Zagni, Nicolò; Puglisi, Francesco Maria; Verzellesi, Giovanni; Pavan, Paolo
abstract

In this work, we present a combined analysis on the statistical variability of threshold voltage, on-state current, and leakage current of III-V ultra-scaled MOSFETs. In addition, we analyze the sensitivity of threshold voltage to critical geometrical and process parameters variations (i.e, gate length, channel thickness, oxide thickness and channel doping). Our analysis verifies the scaling potential of the InGaAs Technology from the variability/sensitivity standpoint for two technologicaTnodes (Lg = 15 nm, Lg = 10.4 nm), by means of Quantum Drift-Diffusion (QDD) simulations. The structure under investigation is a template Dual-Gate Ultra-Thin Body device realized following ITRS projections. The variability sources under consideration are: Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate-Line Edge Roughness (LER). The sensitivity analysis of threshold voltage is performed by considering also the effects of statistical variability to evaluate their combined effect. The results of the statistical variability analysis highlight the importance of carefully controlling Body-LER, as forecasted in the new IRDS report. Moreover, the combined effect of variability and sensitivity to channel thickness are found to be critical to the scaling process (down to Lg =10.4 nm), as it leads to significant leakage increase or performance reduction, potentially resulting in always-on devices.

2016 - A consistent picture of cycling dispersion of resistive states in HfOx resistive random access memory [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo
abstract

In this paper we present the results of a systematic study of resistive states cycling dispersion in HfOx Resistive Random Access Memory (RRAM). A wide set of experimental data is collected on several RRAM devices in different operating conditions. A compact model is exploited lo link the device electrical response to its physical characteristics, delivering a clear physical picture of cycling dispersion and of its sensitivity to operating conditions. The implications of operating voltage, current compliance, and temperature on the device reliability are clarified. Particularly, the dispersion of both RHRS and RLRS is much worsened at low current compliance, which reduces the worst-case read window establishing a trade-off between device reliability and power consumption.

2016 - A multi-scale methodology connecting device physics to compact models and circuit applications for OxRAM technology [Articolo su rivista]
Puglisi, Francesco Maria; Deleruyelle, Damien; Portal, Jean Michel; Pavan, Paolo; Larcher, Luca
abstract

RRAM technology relying on transitional metal oxides (namely OxRAM) is about to reach the industrial stage. Nevertheless the physical-based understanding of the material and process implications at device and circuit levels is still not completely clear, hindering the full industrial exploitation of the OxRAM technology. In this context, this article presents a multi-scale methodology that connects the microscopic material properties to the electrical behavior of OxRAM devices at the circuit level. Microscopic models describing OxRAM operation (i.e., forming, resistive switching) and variability (e.g., cycle-to-cycle, RTN) will be reviewed and used for the development of compact models that will allow investigating the potential of this technology at the circuit level. An overview of some innovative applications involving OxRAM will be finally presented.

2016 - Anomalous random telegraph noise and temporary phenomena in resistive random access memory [Articolo su rivista]
Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper we present a comprehensive examination of the characteristics of complex Random Telegraph Noise (RTN) signals in Resistive Random Access Memory (RRAM) devices with TiN/Ti/HfO2/TiN structure. Initially, the anomalous RTN (aRTN) is investigated through careful systematic experiment, dedicated characterization procedures, and physics-based simulations to gain insights into the physics of this phenomenon. The experimentally observed RTN parameters (amplitude of the current fluctuations, capture and emission times) are analyzed in different operating conditions. Anomalous behaviors are characterized and their statistical characteristics are evaluated. Physics-based simulations considering both the Coulomb interactions among different defects in the device and the possible existence of defects with metastable states are exploited to suggest a possible physical origin of aRTN. The same simulation framework is also shown to be able to predict other temporary phenomena related to RTN, such as the temporary change in RTN stochastic properties or the sudden and iterative random appearing and vanishing of RTN fluctuations always exhibiting the same statistical characteristics. Results highlight the central role of the electrostatic interactions among individual defects and the trapped charge in describing RTN and related phenomena.

2016 - Bipolar Resistive RAM Based on HfO2: Physics, Compact Modeling, and Variability Control [Articolo su rivista]
Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper, we thoroughly investigate the characteristics of the TiN/Ti/HfO/TiN resistive random access memory (RRAM) device. The physical mechanisms involved in the device operations are comprehensively explored from the atomistic standpoint. Self-consistent physics simulations based on a multi-scale approach are employed to achieve a complete understanding of the device physics. The latter includes different charge and ion transport phenomena, as well as structural modifications occurring during the device operations. The main sources of variability are also included by connecting the electrical response of the device to the atomistic material properties. The detailed understanding of the device physics allows developing a physics-based compact model describing the device switching in different operating conditions, including also the effects of cycling variability. Random telegraph noise (RTN), which constitutes an additional variability source, and its relations with cycling variability are analyzed. A statistical link between the programmed resistance and the worst-case RTN effect is found and exploited to include RTN effects in the compact model. Finally, we show how implementing an advanced programming scheme tailored on the device physics allows optimal control over variability and RTN, eventually achieving reliable and RTN-resilient two-bits/cell operations.

2016 - Effects of Border Traps on Transfer Curve Hysteresis and Split-CV Mobility Measurement in InGaAs Quantum-Well MOSFETs [Relazione in Atti di Convegno]
Pavan, Paolo; Zagni, Nicolo'; Puglisi, Francesco Maria; Alian, Alireza; Thean, Aaron Voon Yew; Collaert, Nadine; Verzellesi, Giovanni
abstract

In this paper we present TCAD simulation and experimental results on the influence of interface and border traps on the electrical characteristics of InGaAs quantum-well MOSFETs. These results show that border traps limit the maximum ION, induce a hysteresis in the quasi-static transfer characteristics, and markedly affect CV measurements, inducing a large increase in the accumulation capacitance even at high frequencies where trap effects are commonly assumed to be negligible. The latter effect is particularly insidious from the technologist's perspective, since it can partially compensate quantum capacitance reduction effects, leading to CV data misinterpretation. Interface traps affect mainly the subthreshold slope of IV characteristics and cause frequency dispersion under depletion conditions. Finally, we show that channel mobility extracted by means of the split-CV method is affected by spurious contributions to the gate charge related to both interface and border traps, resulting in channel mobility underestimation.

2016 - Force Impact Effect in Contact-Mode Triboelectric Energy Harvesters: Characterization and Modeling [Relazione in Atti di Convegno]
Lasagni, Marco; Pavan, Paolo; Bertacchini, Alessandro; Larcher, Luca
abstract

In this paper we investigate the effect of the contact force on the voltage generated by Contact-Mode Triboelectric Energy Harvesting Devices (CM-TEHD). The electrical energy harvested from mechanical shocks increases with the contact force. In order to investigate the role of the contact force in the triboelectric energy generation, we developed a physical model, which allows understanding the physical mechanisms of this process, while predicting the output voltage and power at given conditions. Prototypes of the CM-TEHD made of low-cost commercial silicone were fabricated using a very low cost process. The prototypes provide up to 5.5µW when subjected to repetitive impacts with a contact force of 65N.

2016 - Guidelines for a Reliable Analysis of Random Telegraph Noise in Electronic Devices [Articolo su rivista]
Puglisi, Francesco Maria; Pavan, Paolo
abstract

In this paper, we propose new guidelines for the analysis of random telegraph noise (RTN) in electronic devices. Starting from an in-depth understanding of RTN signal characteristics, we will identify the correct measurement conditions to enable RTN analysis as a characterization tool for electronic devices. The estimate of RTN statistical parameters may indeed strongly depend on the choice of measurement conditions. We will carefully consider both the measurement limits and the extraction process constraints to devise a strategy to identify RTN signals measured in conditions allowing a meaningful estimation of their parameters. The proposed strategy will be tested on a variety of different RTN signals and operating conditions.

2016 - Monitoring Stress-Induced Defects in HK/MG FinFETs Using Random Telegraph Noise [Articolo su rivista]
Puglisi, Francesco Maria; Costantini, Felipe; Kaczer, Ben; Larcher, Luca; Pavan, Paolo
abstract

In this letter, we report on nFinFETs degradation during stress exploiting ID and IG noise analysis. We employed a stress/measure approach to monitor device characteristics at different levels of cumulative stress. IG-VG and ID-VG indicators suggest defects generation to occur away from the channel. This is confirmed by the quantitative analysis of ID and IG stationary RTN signals at operating conditions, which show no correlation as opposite to what reported for planar FETs. Moreover, we analyze for the first time the ID-t and IG-t non-stationary instabilities during stress. The results confirm that the generation of defects responsible for SILC occurs away from the channel. Only in highly stressed devices, ID-t and IG-t curves observed during stress exhibit anti-correlation, due to comparable values of the gate and drain current levels originated by the high defect density. Hence, in nFinFETs, ID and IG RTN/instabilities might originate from mechanisms involving different entities.

2016 - Multiscale modeling of electron-ion interactions for engineering novel electronic device and materials [Relazione in Atti di Convegno]
Larcher, Luca; Puglisi, Francesco Maria; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo
abstract

In this work, we present a multiscale simulation platform as a viable tool to engineer novel electron devices. The tool connects the specific material properties (as atomic defects, interfaces, material morphology) to the electrical behavior of the device, representing a virtual space for the design of novel electrons device purposely exploiting atom-electron interactions. This simulation platform is based on the modeling the microscopic interactions and chemical reactions (e.g. bond breaking) between electrons and atomic species (ions, vacancies, dangling bonds). In this work, we show how this tool can be used to design resistive memory devices based on binary oxides. The fundamental importance of the complex interplay between charge carriers and atomic species is highlighted by showing how these interactions determine many electrical characteristics of the device, including charge transport, structural modifications associated with resistive switching, variability, and noise fluctuations.

2016 - Multiscale modeling of electron-ion interactions for engineering novel electronic devices and materials [Relazione in Atti di Convegno]
Larcher, Luca; Puglisi, Francesco Maria; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo
abstract

In this work, we present a multiscale simulation platform as a viable tool to engineer novel electron devices. The tool connects the specific material properties (as atomic defects, interfaces, material morphology) to the electrical behavior of the device, representing a virtual space for the design of novel electrons device purposely exploiting atom-electron interactions. This simulation platform is based on the modeling the microscopic interactions and chemical reactions (e.g. bond breaking) between electrons and atomic species (ions, vacancies, dangling bonds). In this work, we show how this tool can be used to design resistive memory devices based on binary oxides. The fundamental importance of the complex interplay between charge carriers and atomic species is highlighted by showing how these interactions determine many electrical characteristics of the device, including charge transport, structural modifications associated with resistive switching, variability, and noise fluctuations.

2016 - Operations, Charge Transport, and Random Telegraph Noise in HfOx Resistive Random Access Memory: a Multi-scale Modeling Study [Articolo su rivista]
Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this work we explore the mechanisms responsible for Random Telegraph Noise (RTN) fluctuations in HfOx Resistive Random Access Memory (RRAM) devices. The statistical properties of the RTN are analyzed in many operating conditions exploiting the Factorial Hidden Markov Model (FHMM) to decompose the multilevel RTN traces in a superposition of two-level fluctuations. This allows the simultaneous characterization of individual defects contributing to the RTN. Results, together with multi-scale physics-based simulations, allows thoroughly investigating the physical mechanisms which could be responsible for the RTN current fluctuations in the two resistive states of these devices, including also the charge transport features in a comprehensive framework. We consider two possible options, which are the Coulomb blockade effect and the possible existence of metastable states for the defects assisting charge transport. Results indicate that both options may be responsible for RTN current fluctuations in HRS, while RTN in LRS is attributed to the temporary screening effect of the charge trapped at defect sites around the conductive filament.

2016 - Probing defects generation during stress in high-κ/metal gate FinFETs by random telegraph noise characterization [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Costantini, Felipe; Kaczer, Ben; Larcher, Luca; Pavan, Paolo
abstract

In this work, we report about defects generation in the oxide layer of n-FinFETs during stress. Defects generation is probed using RTN traces collected at both the drain and the gate. A stress/measure approach is used to monitor the characteristics of the device, including RTN, at different levels of cumulative stress. Indicators derived from IG-VG and ID-VG measurements suggest defects generation to occur away from the channel. This is confirmed by the RTN analysis, which shows that drain and gate RTN events are completely uncorrelated. The detailed analysis of the RTN properties at different stress levels shows that an increase of the gate leakage is accompanied by changes in the gate RTN properties, while the drain RTN properties are rarely affected by the stress. This further proves that stress is associated with defects generation deep in the oxide layer, far away from the channel. This result is in contrast to what reported for planar FETs and suggests that, in n-FinFETs, the root cause of ID RTN might differ from the one causing SILC and IG RTN.

2016 - Random telegraph noise in HfOx Resistive Random Access Memory: From physics to compact modeling [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Larcher, Luca
abstract

In this paper we propose a compact model of Random Telegraph Noise in HfOx-based Resistive Random Access Memory devices. Starting from the physics of charge transport, we first focus on the RTN phenomenon in the two different resistive states (HRS and LRS). We separately explore the microscopic mechanisms responsible for Random Telegraph Noise (RTN) current fluctuations in HfOx RRAM devices in HRS and LRS, exploiting a self-consistent physics-based simulation framework accounting for many charge transport mechanisms and their alterations. Then, we develop a simple yet effective compact model of RTN valid in both states, which can be easily integrated in state-of-the-art compact RRAM device models. The compact model predictions are validated by comparison with both a large experimental dataset obtained by measuring RRAM devices in different conditions, and data found in the literature.

2016 - Single vacancy defect spectroscopy on HfO2 using random telegraph noise signals from scanning tunneling microscopy [Articolo su rivista]
Thamankar, R.; Raghavan, N.; Molina, J.; Puglisi, Francesco Maria; O'Shea, S. J.; Shubhakar, K.; Larcher, Luca; Pavan, Paolo; Padovani, Andrea; Pey, K. L.
abstract

Random telegraph noise (RTN) measurements are typically carried out at the device level using standard probe station based electrical characterization setup, where the measured current represents a cumulative effect of the simultaneous response of electron capture/emission events at multiple oxygen vacancy defect (trap) sites. To better characterize the individual defects in the high-j dielectric thin film, we propose and demonstrate here the measurement and analysis of RTN at the nanoscale using a room temperature scanning tunneling microscope setup, with an effective area of interaction of the probe tip that is as small as 10 nm in diameter. Two-level and multi-level RTN signals due to single and multiple defect locations (possibly dispersed in space and energy) are observed on 4 nm HfO2 thin films deposited on n-Si (100) substrate. The RTN signals are statis- tically analyzed using the Factorial Hidden Markov Model technique to decode the noise contribu- tion of more than one defect (if any) and estimate the statistical parameters of each RTN signal (i.e., amplitude of fluctuation, capture and emission time constants). Observation of RTN at the nanoscale presents a new opportunity for studies on defect chemistry, single-defect kinetics and their stochastics in thin film dielectric materials. This method allows us to characterize the fast traps with time constants ranging in the millisecond to tens of seconds range.

2016 - System With RF Power Delivery Capabilities for Active Safety Enhancement in Industrial Vehicles Using Interchangeable Implements [Articolo su rivista]
Bertacchini, Alessandro; Napoletano, Giacomantonio; Scorcioni, Stefano; Larcher, Luca; Pavan, Paolo
abstract

In this paper, an active system for safety enhancement in industrial and off-highway vehicles using interchangeable implements is presented. The system, applied to the real case study of automatic identification of implements connected to a telehandler, is developed by adopting a hardware–software codesign approach. It is comprised of two devices: the Illuminator-Gateway Device (IGD) and the End Device (ED). Differently from other similar solutions, the system embeds a complete radio frequency (RF) power delivery system that is compliant with the regulations in force in Europe and in North America to extend the battery lifetime of the ED. In particular, the IGD, positioned on the free end of the telescopic arm of the telehandler, supplies the RF energy required for the operations of the ED and acts as a gateway sending the data received from the ED to the other Electronic Control Units (ECUs) of the vehicle. The ED, instead, is mounted on the connected implement, collects the RF energy delivered by the IGD, and wirelessly sends the unique identifier, the key parameters, and the calculated effective working time of the implement. This information can be used by the main ECU of the vehicle for safety-related purposes and programmed maintenance. Experimental results show that the implemented RF power delivery system is able to gather up to 63% of the power required by the ED when it is on duty, thus significantly extending its battery lifetime.

2015 - A Complete Statistical Investigation of RTN in HfO₂-Based RRAM in High Resistive State [Articolo su rivista]
Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance.

2015 - A Novel Program-Verify Algorithm for Multi-Bit Operation in HfO2 RRAM [Articolo su rivista]
Puglisi, Francesco Maria; Wenger, C.; Pavan, Paolo
abstract

In this letter, we propose a dispersion-aware program-verify algorithm to enable reliable multi-bit operations in HfO2-based RRAM. The significant intrinsic dispersion of the resistive states, typically hindering multi-bit operations, is exploited to devise a program-verify scheme which enables the multi-bit operations with unique properties of failure resilience and adaptability to degradation. We show that an appropriate choice of the algorithm parameters can minimize the average number of cycles needed to program the cell, enabling fast and reliable multi-bit operation. This maximizes the bit/cell ratio and minimizes the dispersion of targeted resistive states.

2015 - A microscopic physical description of RTN current fluctuations in HfOx RRAM [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Vandelli, Luca; Padovani, Andrea; Bertocchi, Matteo; Larcher, Luca
abstract

In this work we explore the microscopic mechanisms responsible for Random Telegraph Noise (RTN) current fluctuations in HfOx Resistive Random Access Memory (RRAM) devices. The statistical properties of the RTN current fluctuations are analyzed in a variety of reading conditions by exploiting the Factorial Hidden Markov Model (FHMM) to decompose the complex RTN traces in a superimposition of two-level fluctuations. We investigate the physical mechanisms that could be responsible for the RTN current fluctuations by considering two options that are the Coulomb blockade effect and the metastable-to-stable transition of defect assisting the Trap- Assisted-Tunneling (TAT) charge transport. Physics-based simulations show that both options allow reproducing the RTN current fluctuations. The electron TAT via oxygen vacancy defects, responsible for the current in High Resistive State (HRS), is significantly altered by the electric field caused by electron trapping at defects (i.e. neutral interstitial oxygen), not directly involved in charge transport. Similarly, the transition of oxygen vacancies into a stable-slow defect configuration (still unidentified in HfOx) can temporarily switch off the current, thus explaining the RTN.

2015 - Characterization of anomalous Random Telegraph Noise in Resistive Random Access Memory [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper we explore the features of complex anomalous Random Telegraph Noise (aRTN) in TiN/Ti/HfO2/TiN Resistive Random Access Memory (RRAM) devices. Careful design of experiment, dedicated characterization techniques, and physics-based simulations are exploited to gain insights into the physics of this phenomenon. The RTN parameters (amplitude of the current fluctuations, capture and emission times) observed in the experiments are analyzed in a variety of operating conditions. Anomalous behaviors are examined and their statistical characteristics are analyzed. Physics-based simulations taking into account both the Coulomb interactions among different defects in the device and the possibility for defects to show metastable states are exploited to suggest a possible origin of the aRTN. Results highlight the importance of the electrostatic interactions among individual defects and the trapped charge.

2015 - Selected papers from ESSDERC 2014 [Articolo su rivista]
Bez, R.; Meneghesso, G.; Pavan, P.; Zanoni, E.
abstract

2015 - Statistical analysis of random telegraph noise in HfO2-based RRAM devices in LRS [Articolo su rivista]
Puglisi, Francesco Maria; Pavan, Paolo; Larcher, Luca; Padovani, Andrea
abstract

In this work, we present a thorough statistical characterization of Random Telegraph Noise (RTN) in HfO2-based Resistive Random Access Memory (RRAM) cells in Low Resistive State (LRS). Devices are tested under a variety of operational conditions. A Factorial Hidden Markov Model (FHMM) analysis is exploited to extrapolate the properties of the traps causing multi-level RTN in LRS. The trapping and de-trapping of charge carriers into/out of defects located in the proximity of the conductive filament results in a shielding effect on a portion of the conductive filament, leading to the observed RTN current fluctuations. It is found that both oxygen vacancies and oxygen ions defects may be responsible for the observed RTN. The variations of the current observed at subsequent set/reset cycles are instead attributed to the stochastic variations in the filament due to oxidation/reduction processes during reset and set operations, respectively.

2015 - Temperature impact on the reset operation in HfO2 RRAM [Articolo su rivista]
Puglisi, Francesco Maria; Qafa, Altin; Pavan, Paolo
abstract

In this letter we report about the impact of temperature on the reset process in HfO2 RRAM devices. I-V analysis of the device during consecutive switching cycles in different operating conditions and temperatures is performed. A compact model is exploited to extrapolate the properties of the conductive filament after the reset operation. The different temperature dependences of the reset process and the charge transport in High Resistive State are taken into account: by extracting the effective activation energy of the charge transport in High Resistive State, we are able to estimate the effect of temperature on the reset process. A linear relation is found between barrier thickness and reset temperature. High temperature switching may improve cycling variability at ultra- low reset voltage.

2015 - Ultra low cost triboelectric energy harvesting solutions for embedded sensor systems [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Larcher, Luca; Lasagni, Marco; Pavan, Paolo
abstract

In this paper we present a triboelectric generator realized with ultra-low cost materials, assembled through a very simple in-house fabrication facility. The triboelectric generator is designed to harvest the mechanical energy from shocks. Different combinations of low-cost materials such as acetic, neutral and acrylic silicone was explored to increase device performances. The device prototypes, characterized under various working conditions show a generated output power of 25µW with an applied load of 50 MΩ, which makes this technology solution very attractive for embedded energy-autonomous sensors system solutions.

2014 - A Compact Model of Program Window in HfOx RRAM Devices for Conductive Filament Characteristics Analysis [Articolo su rivista]
Larcher, Luca; Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Vandelli, Luca; Bersuker, Gennadi
abstract

This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices.

2014 - A study on HfO2 RRAM in HRS based on I–V and RTN analysis [Articolo su rivista]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca
abstract

This paper presents a statistical characterization of random telegraph noise (RTN) in hafnium-oxide based resistive random access memories (RRAMs) in high resistive state (HRS). Complex RTN signals are analyzed exploiting a Factorial Hidden Markov Model (FHMM) approach, which allows to derive the statistical properties of the RTN signals, directly related to the physical properties of the traps responsible for the multi-level RTN measured in these devices. Noise characteristics in different reset conditions are explored through consecutive switching cycles. Noise spectral analysis is also performed to fully support the investigation. An RRAM compact model is also exploited to estimate the physical properties of the conductive filament and of the dielectric barrier from simple I–V data. These tools are combined together to prove the existence of a direct statistical relation between the reset conditions, the volume of the dielectric barrier created during the reset operation and the average number of active traps contributing to the RTN.

2014 - Active Safety System with RF Energy Harvesting Capabilities for Industrial Applications using Interchangeable Implements [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Napoletano, Giacomantonio; Scorcioni, Stefano; Larcher, Luca; Pavan, Paolo
abstract

In this paper a system for the remote powering of low power electronic devices is presented. The system has been applied to a real industrial application allowing to enhance active safety in industrial vehicles. It is comprised of two main devices: i) the End Device (ED) with an embedded Radio Frequency (RF) energy harvester; ii) the Illuminator-Gateway Device (IGD) with an embedded RF power transmitter. Thanks to the optimization of the customized dual band Planar Inverted Folded Antenna (PIFA) used, the ULP architecture of the ED, the hardware-software co-design approach used and the optimization of the ED firmware, the proposed system is able to provide up to the 63% of the power required by the ED when it is on duty.

2014 - An investigation on the role of current compliance in HfO2-based RRAM in HRS using RTN and I-V data [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo
abstract

In this paper we investigate the effect of current compliance during forming in HfO2-based Resistive Random Access Memories (RRAMs). We implemented a thorough statistical characterization of Random Telegraph Noise (RTN) in High Resistive State (HRS). Complex RTN signals are analyzed through a Factorial Hidden Markov Model (FHMM) approach, deriving the statistical properties of traps responsible for the multi-level RTN measured in these devices. Noise is explored in devices formed at different current compliances, demonstrating a direct relation between the current compliance, the cross-section of both the CF and the dielectric barrier created during the reset operation, and the number of active traps contributing to the RTN.

2014 - Analysis of RTN and cycling variability in HfO2 RRAM devices in LRS [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Larcher, Luca; Padovani, Andrea
abstract

In this work, we present a thorough statistical characterization of cycling variability and Random Telegraph Noise (RTN) in HfO2-based Resistive Random Access Memory (RRAM) cells in Low Resistive State (LRS). Devices are tested under a variety of operational conditions. A Factorial Hidden Markov Model (FHMM) analysis is exploited to extrapolate the properties of the traps causing multi-level RTN in LRS. The trapping and de-trapping of charge carriers into/out of defects located in the proximity of the conductive filament results in a shielding effect on a portion of the conductive filament, leading to the observed RTN current fluctuations. The variations of the current observed at subsequent set/reset cycles are instead attributed to the stochastic variations in the filament due to oxidation/reduction processes during reset and set operations, respectively. The statistical characterization of RTN and cycling variability does not show correlation between these phenomena.

2014 - Defect density evaluation in a high-k MOSFET gate stack combining experimental and modeling methods [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Veksler, D.; Matthews, K.; Bersuker, G.; Larcher, Luca; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo
abstract

We report on a methodology to assist fabrication process development using a case study of high thermal budget (HTB) and low thermal budget (LTB) fabrication flows for high- k/metal gate stacks in n-MOSFETs. This methodology is supported by simulations that self-consistently extract defect characteristics by simultaneously considering a set of electrical measurement data, specifically stress-induced leakage current (SILC), threshold voltage shift (PBTI), and multi-frequency charge-pumping (MFCP). The contributions of pre-existing and stress-induced defects in SiO2/HfO2 gate stacks on device performance are examined. Information on defect distributions, extracted in the as-fabricated and post-stress HTB and LTB devices, allow understanding their dependence on the fabrication process, which can provide guidelines for the process optimization.

2014 - Factorial Hidden Markov Model analysis of Random Telegraph Noise in Resistive Random Access Memories [Articolo su rivista]
Puglisi, Francesco Maria; Pavan, Paolo
abstract

This paper presents a new technique to analyze the characteristics of multi-level random telegraph noise (RTN). RTN is dened as an abrupt switching of ei- ther the current or the voltage between discrete values as a result of trapping/de-trapping activity. RTN sig- nal properties are deduced exploiting a factorial hid- den Markov model (FHMM). The proposed method considers the measured multi-level RTN as a super- position of many two-levels RTNs, each represented by a Markov chain and associated to a single trap, and it is used to retrieve the statistical properties of each chain. These properties (i.e. dwell times and amplitude) are directly related to physical properties of each trap.

2014 - Instability of HfO2 RRAM devices: Comparing RTN and cycling variability [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Larcher, Luca; Pavan, Paolo; Padovani, Andrea; Bersuker, G.
abstract

In this study, we present an extensive statistical characterization of the cycling variability and Random Telegraph Noise (RTN) in the HfO2-based Resistive Random Access Memories (RRAM) cells. Devices with different dielectric stacks are tested under a variety of read (sampling times and read voltage magnitudes) and operational (reset voltages) conditions. A Factorial Hidden Markov Model (FHMM) analysis is employed to reveal the properties of the traps causing multi-level RTN in High Resistive State (HRS), while the I-V data are analyzed through the developed compact model to investigate cycling variability. The activation and deactivation of traps assisting the charge transport through a dielectric barrier in HRS is found to be responsible for the observed RTN while the read current variations can be attributed to the stochastic nature of the filament oxidation process during reset, also leading to a variable number of traps formed in the barrier after each switching cycle. The statistical characterization of RTN and cycling variability, which demonstrates the uncorrelated nature of these phenomena, provides guidelines for scaling and optimization of RRAM device operations and reliability.

2014 - On the limitations of transipedance amplifiers as tools for low-frequency noise characterization [Articolo su rivista]
Borgarino, Mattia; BETTI BENEVENTI, Giovanni; Doga, Valerio; Pavan, Paolo
abstract

An experimental set-up for the characterization of low-frequency noise on two terminal devices is reported. The experimental set-up is based on the use of the commercial transimpedance amplifier (TA) EG&G5182. This paper addresses the influence of the TA on the noise characterization process by describing the TA as a non-ideal operational amplifier with a feedback resistor. The impact of the TA finite input resistance and voltage gain is highlighted through comparison with measurements carried out on resistors and diodes.

2014 - Optimized Energy-Aware Wireless System for Identification of the Relative Positioning of Articulated Systems in the Free Space [Articolo su rivista]
Bertacchini, Alessandro; Napoletano, Giacomantonio; Dondi, Denis; Larcher, Luca; Pavan, Paolo
abstract

In this paper, a low-cost solution to identify the relative positioning of articulated systems in the free space is presented. To prove the effectiveness of the proposed solution, the system has been applied to a real case study of a tractor connected with a baler. Differently from other solutions, the implemented system can monitor the working conditions of the whole machinery while warning the driver when the machinery gets into a dangerous situation. The system is comprised of two wireless devices called Wireless Master Device (WMD) and Wireless End Device (WED) installed on the tractor and on the baler, respectively. To identify instantaneously the dangerous working conditions, each of the two wireless devices exploits a MEMS inertial sensor measuring 3-D linear accelerations and 3-D magnetic fields components integrated in the devices. Very low power consumption has been obtained by exploiting a hardware–software codesign approach implementing an optimized algorithm combined with a smart task manager. Furthermore, a vibrational energy harvester has been designed and integrated on the WED in order to make the device autonomous from an energetic point of view.

2014 - Progresses in Modeling HfOx RRAM Operations and Variability [Relazione in Atti di Convegno]
Larcher, Luca; Pirrotta, Onofrio; Puglisi, Francesco Maria; Padovani, Andrea; Pavan, Paolo; Vandelli, Luca
abstract

This paper reports on recent progresses in modeling bi-polar RRAM devices based on hafnium oxide. The unique modeling environment adopted for the simulation of device operations accounts self-consistently for the charge and ion transport, and the structural device modification occurring during forming and set/reset operations. Reliability mechanisms as well as the major sources of devices variability are included thanks to a multi-scale approach that connects the electrical device performance to the atomic-level material properties. The modeling methodology can be successfully applied to both improve device performances and fabrication process of state-of-the-art RRAM devices, and devise device solutions for future 3D RRAM architectures.

2014 - Welcome to ESSDERC 2014 [Relazione in Atti di Convegno]
Meneghesso, G.; Bez, R.; Pavan, P.
abstract

2013 - A Compact Model of Hafnium-Oxide-Based Resistive Random Access Memory [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca
abstract

In this paper, a compact model of hafnium-oxide-based resistive random access memory (RRAM) cell is developed. The proposed model includes the effect of the temperature and cycle-to-cycle stochastic variations affecting the device operations. Simple I-V measurements are used to extract the model parameters. The model accurately reproduces the I-V curves of the switching cycles in different operating conditions.

2013 - An Empirical Model for RRAM Resistance in Low- and High-Resistance State [Articolo su rivista]
Puglisi, Francesco Maria; Larcher, Luca; G., Bersuker; Padovani, Andrea; Pavan, Paolo
abstract

We present a simple empirical expression describing hafnium-based RRAM resistance at different reset voltages and current compliances. The model that we propose describes filament resistance measured at low (∼0.1 V) reading voltage in both low-resistance state (LRS) and high-resistance state (HRS). The proposed description confirms that conduction in LRS is ohmic (after forming with a sufficiently high current compliance) and is consistent with the earlier description of HRS resistance as controlled by a trap-assisted electron transfer via traps in the oxidized portion of the filament. The length of the nonohmic part of the filament is found to be directly proportional to reset voltage. Moreover, low-frequency noise measurements at different reset voltages evidence a tradeoff between HRS resistance and noise in reading conditions.

2013 - Charge Transport and Degradation in HfO2 and HfOx Dielectrics [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; Gennadi, Bersuker; Pavan, Paolo
abstract

We combine experiments and simulations to investigate leakage current and breakdown (BD) in stoichiometric and sub-stoichiometric hafnium oxides. Using charge-transport simulations based on phonon-assisted carrier tunneling between trap sites, we demonstrate that higher currents generally observed in HfOx are due to a higher density of the as-grown oxygen vacancy defects assisting the charge transport. Reduction of the dielectric breakdown field (EBD) in HfOx is explained by the lower zero-field activation energy (EA,G) of the defect generation process, as extracted from time-dependent dielectric breakdown experiments.

2013 - Compact modeling of TANOS program/erase operations for SPICE-like circuit simulations [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

We present an analytical model of TANOS program/erase transients that can be used to implement a compact SPICE-like model of these memory devices. Simulation results obtained from a physics-based TANOS model are used to derive simple analytical formulas relating the program/erase currents and the centroid of the trapped charge distribution to operating conditions and stack composition. The model allows reproducing with a good agreement the experimental program/erase transients, thus providing a valuable tool for IC designers to optimize TANOS memory circuits, especially in the framework of multi-level applications.

2013 - FHMM analysis for Multi-Defect Spectroscopy in HfOX RRAM [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo
abstract

This paper presents a new technique to analyze the characteristics of multi-level random telegraph noise (RTN) in HfOX RRAM. RTN is characterized by abrupt switching of either the current or the voltage between discrete values as a result of trapping/de-trapping activity while reading the RRAM cell. RTN statistical properties are deduced exploiting a factorial hidden Markov model (FHMM). The proposed method considers the measured multi-level RTN as a superposition of many two-levels RTN, each represented by a Markov chain and associated to a single trap, and it is used to retrieve the statistical properties of each chain. These properties (i.e. dwell times and amplitude) are directly related to physical properties of each trap

2013 - Perimeter and area current components in HfO2 and HfO2-x metal-insulator-metal capacitors [Articolo su rivista]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca
abstract

In this paper, the authors present an experimental analysis on current conduction mechanisms in high-k oxides, where two metal–insulator–metal structures with different insulators (HfO2 and HfO2-x) are considered. Current density measurements indicate the existence of a perimeter-related component in the current, sizeable in HfO2, and negligible in HfO2-x samples, which have to be taken into account for a correct analysis of the device behavior and cannot be based only on the area scaling rules. For oxide breakdown, for example, a significant contribution of the perimeter-related current component results in conservative extrapolations of breakdown voltages for scaled devices.

2013 - RTN analysis with FHMM as a tool for multi-trap characterization in HfOx RRAM [Relazione in Atti di Convegno]
PUGLISI, Francesco Maria; PAVAN, Paolo
abstract

This paper presents a new technique to analyze the characteristics of multi-level random telegraph noise (RTN) in HfOX RRAM. RTN is characterized by abrupt switching of either the current or the voltage between discrete values as a result of trapping/de-trapping activity while reading the RRAM cell. RTN statistical properties are deduced exploiting a factorial hidden Markov model (FHMM). The proposed method considers the measured multi-level RTN as a superposition of many two-levels RTN, each represented by a Markov chain and associated to a single trap, and it is used to retrieve the statistical properties of each chain. These properties (i.e. dwell times and amplitude) are directly related to physical properties of each trap.

2013 - RTS Noise Characterization of HfOx RRAM in High Resistive State [Articolo su rivista]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca; G., Bersuker
abstract

In this paper we analyze Random Telegraph Signal (RTS) noise cand Power Spectral Density (PSD) in hafnium-based RRAMs. RTS measured in HRS exhibits fast and slow multilevel switching events. RTS characteristics are examined through novel color-coded time-lag plots and Hidden Markov Model (HMM) time-series analyses. Results are validated by comparing simulated and experimental PSD. Noise is examined at different reset conditions to provide an insight into the conduction mechanisms in HRS. Higher reset voltages are found to result in greater RTS complexity due to a larger number of active traps as confirmed by PSD.

2013 - Random Telegraph Noise analysis to investigate the properties of active traps of HfO2-Based RRAM in HRS [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca
abstract

This paper presents statistical characterization of Random Telegraph Noise (RTN) in hafnium-oxide-based Resistive Random Access Memories (RRAMs) in High Resistive State (HRS). Complex RTN signals are analyzed exploiting a Factorial Hidden Markov Model (FHMM) approach, allowing to derive the statistical properties of traps responsible of the multi-level RTN measured in these devices. Noise characteristics in different reset conditions are explored to prove the existence of a direct relation between the reset voltage, the volume of the dielectric barrier created during the reset operation and the number of active traps contributing to the RTN.

2012 - A WSN System Powered by Vibrations to Improve Safety of Machinery with Trailer [Relazione in Atti di Convegno]
Dondi, Denis; Napoletano, Giacomantonio; Bertacchini, Alessandro; Larcher, Luca; Pavan, Paolo
abstract

In this paper we present an energetically autonomous wireless sensor system designed to enhance safety in industrial machinery comprising a main vehicle with an attached trailer. The proposed system establishes a wireless link between the vehicle ECU and our sensors to provide motion dynamic data of trailer to the vehicle stability control algorithm. The wireless sensor devices we implemented comprise a 3-axial accelerometer and a 3-axial magnetometer to detect the trailer operating conditions. Such motion data are elaborated using an ultra-low power MCU, which communicates to vehicle’ ECU using an IEEE 802.15.4 channel at 2.4GHz. To enable perpetual operation of the system, we developed a vibrational energy harvesting system, VIBester, capable to gather kinetic energy from trailer natural vibrations and convert such energy in electrical energy for the system power supply. The vibrational energy harvester adopts a piezoelectric (PZT) transducer to convert the kinetic energy and a custom AC/DC converter to supply the wireless sensor device.

2012 - An autonomous wireless sensor network device powered by a RF energy harvesting system [Relazione in Atti di Convegno]
Dondi, Denis; Scorcioni, Stefano; Bertacchini, Alessandro; Larcher, Luca; Pavan, Paolo
abstract

In this paper, we present an energetically autonomous wireless sensor network (WSN) device designed to enhance safety in vehicles capable to connect extra gear/equipment to the main chassis. The proposed system allows the vehicle stability control system to automatically recognize the connected trailer or implement through a purposely designed WSN device, which is integrated into trailer /implement and wirelessly sends its identification number. The WSN device we developed integrates also a novel RF energy harvesting circuit which gathers the energy from an 868MHz RF signal source, which is purposely transmitted from the vehicle towards the trailer or implement for remote powering. Measurements performed on fabricated WSN system prototypes show that the RF harvester can gather up to ≈50uW@3m from the RF power source with efficiency higher than 30% over a range of 10dBm. The combination of the RF energy harvesting circuit with the ultra-low power architecture and a custom task manager designed for the WSN system allows to further increase primary battery lifetime, making the wireless system capable to operate autonomously for several years.

2012 - Assessment of self-induced Joule-heating effect in the I − V readout region of polycrystalline Ge2Sb2Te5 Phase-Change Memory [Articolo su rivista]
G., Betti Beneventi; L., Perniola; Q., Hubert; A., Glière; Larcher, Luca; Pavan, Paolo; B., De Salvo
abstract

The physical mechanisms that regulate carrier transportin polycrystalline chalcogenides, such as Ge2Sb2Te5 (GST),are still debated. Recently, self-induced Joule-heating (SJH) effecthas been claimed to be the key factor in explaining the nonlinearityof the I–V characteristics of polycrystalline GST-basedphase-change memory (PCM). In this paper, we carefully investigatethe SJH occurring in the GST material by analyzing theI–V characteristics of PCM cells at low voltages, i.e., in thememory-cell readout region. To accomplish the study, we usead hoc fabricated PCM devices allowing an easier evaluationof SJH occurring in the chalcogenide layer. A novel procedureto test the SJH effect is also proposed. A comparison betweennumerical simulations and compact modeling is discussed as well.Our paper shows that the SJH effect is not sufficient to reproducethe experimental I–V nonlinearity, claiming for new experimentsand theoretical investigations. Therefore, this paper can be considereda step forward toward the comprehension of the transportproperties of polycrystalline GST, which is a key aspect for robustmodeling of PCM devices.

2012 - Enhancing Safety in Vehicles with Implement or Trailer using an Autonomous Wireless Sensor Network System [Relazione in Atti di Convegno]
Dondi, Denis; Bertacchini, Alessandro; Scorcioni, Stefano; Larcher, Luca; Pavan, Paolo
abstract

In this paper, we present an autonomous wireless sensor network system to enhance safety in vehicles with connected implement or trailer. Today’s vehicle stability control algorithms are used to enhance safety and prevent accidents, but they do not take into account if a trailer or an implement is connected to the front/rear of the vehicle. The proposed system allows overcoming this limitation by advertising to the vehicle’ electronic control unit the presence of the connected implement. This allows the stability control algorithm adjusting the vehicles parameters to current real conditions. The developed system comprises two wireless devices: a Wireless Master Device (WMD), mounted on the vehicle, and an autonomous Wireless End Device (WED), installed on the connected implement or trailer. The WED gathers energy from implement’ or trailer’ natural vibrations by using a vibrational energy harvester and a piezoelectric transducer. Thus, avoiding the need of frequent battery replacement and leading the wireless system to autonomously work for several years.

2012 - Leakage current in HfO2 stacks: from physical to compact modeling [Relazione in Atti di Convegno]
Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper we discuss the physical mechanisms governing the charge transport inside hafnium based dielectric stack from a modeling perspective. We propose a detailed Monte-Carlo physical model, which describes the charge transport across high-k stacks through the multiphonon trap-assisted-tunneling theory. This model reproduces accurately the voltage and temperature dependencies of the leakage current across HfO2-based stacks. Starting from this physical description, we develop an analytical model for the TAT current across high-k stacks, which can be implemented into SPICE-like circuit simulators. Despite the simplifying approximations, this compact model reproduces accurately the measurements, thus representing an effective tool for the investigation of the TAT currents.

2012 - RF to DC CMOS rectifier with high efficiency over a wide input power range for RFID applications [Relazione in Atti di Convegno]
Scorcioni, Stefano; Bertacchini, Alessandro; Larcher, Luca; Ricciardi, Antonio; Dondi, Denis; Pavan, Paolo
abstract

In this paper we present a RF-DC rectifier which operates over a wide range of input power by providing a regulated output DC voltage. The circuit solution we propose is based on a novel active load circuit which adjusts the output current as a function of the incoming RF power. This allows maximizing both the efficiency and sensitivity of the circuit. Circuit prototypes fabricated in 130nm CMOS technology start to operate at -14dBm, providing a regulated output voltage of 1.6÷1.8V in the -14÷1dBm RF input power at 868MHz. Noticeably, the circuit efficiency of the rectifier peaks at 45%, remaining above 30% in the -12÷+1dBm input power range.

2012 - Random Telegraph Signal Noise Properties of HfOx RRAM in High Resistive States [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca; G., Bersuker
abstract

In this paper we analyze Random Telegraph Signal (RTS) noise in hafnium-based RRAMs. RTS is measured in HRS, showing fast and slow multilevel switching events. RTS characteristics are examined through novel color-coded time-lag plots and Hidden Markov Model (HMM) time-series analyses. Noise is examined at different reset conditions to provide new insights on conduction mechanisms in HRS. Higher reset voltages result in an enhanced complexity in RTS due to a larger number of active traps

2012 - Understanding the Role of the Ti Metal Electrode on the Forming of HfO2-based RRAMs [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo; C., Cagli; B., de Salvo
abstract

In this paper we investigate in details the effects of the Ti metal electrode on the forming operation in HfO2 RRAM devices. Starting from electrical data and physico-chemical analysis, we use physics-based RRAM modeling to understand the physics governing the CF formation in RRAM stacks with Ti electrodes. Simulations show that the lower forming voltage typically observed in these devices is due to the Ti-induced formation of a sub-stoichiometric HfOx region in the resistive switching layer. The model allows extracting the characteristics of this sub-stoichiometric region that are crucial for developing future low-voltage RRAM devices.

2011 - A Comprehensive Understanding of the Erase of TANOS Memories Through Charge Separation Experiments and Simulations [Articolo su rivista]
Padovani, Andrea; A., Arreghini; Vandelli, Luca; Larcher, Luca; G., Van den Bosh; Pavan, Paolo; J., Van Houdt
abstract

We investigate and quantify the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations. Results demonstrate that electron emission via trap to-band tunneling dominates the first part of the erase operation, whereas hole injection prevails in the remaining part of the transient. In addition, we show that the efficiency of the erase operation is high and constant mainly because of the high energy offset between nitride and alumina valence bands. Our results clearly identify the physical mechanisms responsible for TANOS erase and allow deriving some important guidelines for the optimization of this operation.

2011 - A Physics-Based Model of the Dielectric Breakdown in HfO2 for Statistical Reliability Prediction [Relazione in Atti di Convegno]
Vandelli, Luca; G., Bersuker; Padovani, Andrea; J. H., Yum; Larcher, Luca; Pavan, Paolo
abstract

We present a quantitative physical model describingthe current evolution due to the formation of a conductivefilament responsible for the HfO2 dielectric breakdown. Bylinking the microscopic properties of the stress-generatedelectrical defects to the local power dissipation and to thecorresponding temperature increase along the conductive paththe model reproduces the rapid current increase observed duringthe breakdown. The model successfully simulates theexperimental time-dependent dielectric breakdown distributionsmeasured in HfO2 MIM capacitors under constant voltage stress,thus providing a statistical reliability prediction capability, whichcan be extended to other high-k materials, multilayer stacks,resistive memories based on transition metal oxides, etc.

2011 - A Vibration-Powered Wireless System to Enhance Safety in Agricultural Machinery [Relazione in Atti di Convegno]
Scorcioni, Stefano; Bertacchini, Alessandro; Dondi, Denis; Larcher, Luca; Pavan, Paolo; G., Mainardi
abstract

In this paper, we present a wireless sensing system capable to enhance safety in agricultural machinery. Modern farm tractors adopt vehicle stability control algorithms to enhance safety and prevent accidents. The main limitation in current approach is that the tractor has no information about the implement connected on the front/rear. The system we propose provides information on the connected implement to the tractor control unit allowing the vehicle characteristics update, which allows enhancing vehicle safety. The system we developed is comprised of two wireless devices. The first one, called Master Device (MD), is mounted on the tractor and receives power supply from on-board electrical system. The second one, called End-Device (ED), is mounted on the implement and gathers the supply energy from implement natural vibrations by using a vibrational energy harvester and a piezoelectric transducer. With this approach, the device can recharge an energy reservoir (e.g. a battery) during the implement usage, thus avoiding the need of frequent battery replacement and leading the wireless system to autonomously work for several years.

2011 - AlN-based MEMS devices for vibrational energy harvesting applications [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Scorcioni, Stefano; Dondi, Denis; Larcher, Luca; Pavan, Paolo; M. T., Todaro; A., Campa; G., Caretto; S., Petroni; A., Passaseo; M., De Vittorio
abstract

This paper presents a new AlN-based MEMS devices suitable for vibrational energy harvesting applications. Due to their particular shape and unlike traditional cantilever which efficiently harvest energy only if subjected to stimulus in the proper direction, the proposed devices have 3D generation capabilities solving the problem of device orientation and placement in real applications. Thanks to their particular shape, the realized devices present more than one fundamental resonance frequencies in a range comprised between 500 Hz and 1.5 kHz, with a voltage generation higher than 300μV and an output power up to 0.4 pW for single MEMS device.

2011 - Carbon-doped GeTe: A promising material for Phase-Change Memories [Articolo su rivista]
G., Betti Beneventi; L., Perniola; V., Sousa; E., Gourvest; S., Maitrejean; J. C., Bastien; A., Bastard; B., Hyot; A., Fargeix; C., Jahan; J. F., Nodin; A., Persico; A., Fantini; D., Blachier; A., Toffoli; S., Loubriat; A., Roule; S., Lhostis; H., Feldis; G., Reimbold; T., Billon; B., De Salvo; Larcher, Luca; Pavan, Paolo; D., Bensahel; P., Mazoyer; R., Annunziata; P., Zuliani; F., Boulanger
abstract

This paper investigates Carbon-doped GeTe (GeTeC) as novel material for Phase-Change Memories (PCM). In the first part of the manuscript, a study of GeTeC blanket layers is presented. Focus is on GeTeC amorphous phase stability, which has been studied by means of optical reflectivity and electrical resistivity measurements, and on GeTeC structure and composition, analyzed by XRD and Raman spectroscopy. Then, electrical characterization of GeTeC-based PCM devices is reported: resistance drift, data retention performances, RESET current and power, and SET time have been investigated. Very good data retention properties and reduction of RESET current make GeTeC suitable for both embedded and stand-alone PCM applications, thus suggesting GeTeC as promising candidate to address some of the major issues of today’s PCM technology.

2011 - Charge transport in high-k stacks for charge-trapping memory applications: A modeling perspective (invited) [Articolo su rivista]
Larcher, Luca; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo
abstract

Charge trapping (CT) memories could be a promising technology option for further NAND Flash scaling. The assessment of the scalability limits and ultimate performances of this technology demands for the comprehensive understanding of the physical mechanisms governing device operation and reliability, which requires accurate physics-based models reproducing the electrical device characteristics. The basic features of the models presented in the literature for CT memory devices are reviewed, underlining theirsimilarities and differences, and highlighting their importance in order to achieve a comprehensive understanding of the physical mechanisms responsible for CT device operation and reliability. A physical model describing the charge transport in nitride and high-j stacks is also presented, which allows gaining further insights into reliability issues related to charge localization and high-j tunnel and blocking dielectrics, like the effects of the blocking alumina layer and the band-gap engineered tunnel dielectrics on the TANOS device retention.

2011 - Charge trapping in alumina and its impact on the operation of metal-alumina-nitride-oxide-silicon memories: experiments and simulations [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; DELLA MARCA, Vincenzo; Pavan, Paolo; H., Park; G., Bersuker
abstract

We investigate electron/hole trapping phenomena in alumina blocking oxide and their impact on the program/erase operations and retention of TANOS memory devices. For this purpose, we perform simulations using a physical model reproducing charge injection/trapping in TANOS devices, which is extended to account for the charge trapping phenomena in the blocking layer. We derive the electrical characteristics of both electron and hole traps in Al2O3 by reproducing the measured program, erase and retention transients. Our results show that the amount of electron charge trapped in the alumina during a program operation strongly depends on the stack composition and program voltages and can account for up to 25% of the total threshold voltage shift, whereas hole trapping during erase is negligible. Finally, we investigate the degradation of retention caused by the electron trapping in the alumina blocking layer, which is shown to result in accelerated charge loss.

2011 - Comprehensive physical modeling of forming and switching operations in HfO2 RRAM devices [Relazione in Atti di Convegno]
Vandelli, Luca; Padovani, Andrea; Larcher, Luca; G., Broglia; G., Ori; Montorsi, Monia; G., Bersuker; Pavan, Paolo
abstract

In this work we apply a physical model based on charge transport and molecular mechanics/dynamics simulations to investigate the physical mechanisms governing the RRAM forming and switching operations. The proposed model identifies the major driving forces controlling conductive filament (CF) formation and changes during RRAM switching, thus providing a tool for investigation and optimization of RRAM devices.

2011 - Experimental/numerical investigation of buried-channel InGaAs MOS-HEMTs with Al2O3 gate dielectric [Relazione in Atti di Convegno]
Morassi, Luca; Verzellesi, Giovanni; Pavan, Paolo; D., Veksler; I., Ok; H., Zhao; J. C., Lee; G., Bersuker
abstract

We analyze the electrical behavior of buried-channel InGaAs MOS-HEMTs with Al2O3 gate dielectric by means of measurements and numerical device simulations, with the aim of pointing out peculiar aspects that can be critical for device design/optimization purposes. Our analysis focuses in particular on effects associated with traps at the dielec-tric/barrier interface and unintentional doping in the buffer layer, showing their combined impact on crucial device pa-rameters like threshold voltage, subthreshold slope and drain-bias dependence of subthreshold drain current.

2011 - Modeling of the forming operation in HfO2-base resistive switching memories [Relazione in Atti di Convegno]
Vandelli, Luca; Padovani, Andrea; Larcher, Luca; G., Bersuker; D., Gilmer; Pavan, Paolo
abstract

This paper presents a novel physical description of the forming process in HfO2-based resistive switching memory devices (RRAM). By taking into consideration a grain boundary-driven trap-assisted electron transport and accounting for the local power dissipation and the associated local temperature increase, which assists defect generation, the model reproduces quantitatively the evolution of the leakage current observed during the forming operation in the RRAM devices. The model statistical capabilities allow reproducing the statistical distribution of the forming voltage, thus providing a powerful tool for the assessment of the feasibility of these devices for high-capacity non-volatile memory mass storage applications

2011 - Modeling strategies for flash memory devices [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

In this paper, we will review the modeling strategies for standard and advanced Flash memory devices based on Floating Gate devices developed by our research group in the last ten years. We will show a complete compact model that includes program/erase and leakage currents that can be used to simulate memory cells in both DC (read operation) and transient conditions (Program/Erase). The same model can be used also for reliability simulations by providing good descriptions of the degradation mechanisms. We will also show the extended model for circuit simulation of NAND strings, modified to account for capacitive coupling effects. Finally, we will show how the same framework can be used to develop a compact model for operations of advanced planar charge-trapping memory devices.

2011 - Modeling the charge transport and degradation in HfO 2 dielectric for reliability improvement and life-time predictions in logic and memory devices [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Vandelli, Luca; Pirrotta, Onofrio; Pavan, Paolo
abstract

HfO2 is currently used in the gate stacks of CMOS logic devices and is widely investigated for its potential application in advanced non-volatile memories such as resistive switching devices (RRAMs). In both applications, the understanding of the physical mechanisms governing the charge transport and the degradation/breakdown (BD) of the dielectric is fundamental to optimize device operation and reliability, and represents the first step toward accurate lifetime predictions. These goals can be achieved through the development of accurate physics-based models linking the microscopic properties of HfO2 to the electrical behavior of the device. We show the model we developed for the charge transport and degradation in HfO2 and its application to logic and memory devices.

2010 - 250mV Input Boost Converter for Low Power Applications [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Scorcioni, Stefano; Cori, Marco Maria; Larcher, Luca; Pavan, Paolo
abstract

This paper presents a novel low power boost converter designed and optimized to operate with a minimum input voltage as low as 250mV, which is the typical voltage range of novel micro energy sources. The low power budget of such energy sources (at most few hundreds of μWs) mandates the adoption of very efficient circuit solutions. The realized PCB prototype provides a regulated maximum output voltage 3.3V with 70% maximum efficiency, thus making the proposed converter topology very attractive for low power application power supply. Noticeably the converter operates without any external power supply of the control logic.

2010 - A Micro Fuel Cell Power Supply Module for Low Power Portable Applications [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Scorcioni, Stefano; Cori, Marco Maria; Larcher, Luca; Pavan, Paolo; J. P., Esquivel; N., Torres Herrero; N., Sabaté; J., Santander
abstract

This paper presents a power supply module targeted for low-power applications in the sub-mW range incorporating a passive µDMFC fuel cell (µFC) acting as energy source and a customized boost converter for the energy conversion. The low power budget of such energy sources mandates the adoption of efficient circuit solutions, hence the design of the boost converter is challenging. To maximize the lifetime of the micro fuel cell, the module has been designed to keep constant the µFC operating point and it has been optimized to work with µFC providing a voltage in the range 280mV-320mV, reaching a maximum efficiency higher than 65% with an output power of 350 μW.

2010 - Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs [Relazione in Atti di Convegno]
Morassi, Luca; Verzellesi, Giovanni; Padovani, Andrea; Larcher, Luca; Pavan, Paolo; D., Veksler; Injo, Ok; G., Bersuker
abstract

Interface-trap effects are analyzed in inversion-type, self-aligned In0.53Ga0.47As and In0.53Ga0.47As/In0.2Ga0.8As MOSFETs with ALD ZrO2 gate dielectric. Interface-trap densities in the order of 1e13 cm-2 eV-1 are required to explain the measured subthreshold slopes. For these Dit values, donor-like interface traps are compatible with threshold-voltage values in the 0-0.15 V range as those observed in these devices. Moreover, the presence of donor-like interface traps can explain the negative threshold-voltage shift induced by the inclusion of the In0.2Ga0.8As cap layer, as the result of the influence of interface traps located at the In0.2Ga0.8As/ZrO2 interface on the inversion channel forming at the In0.53Ga0.47As/In0.2Ga0.8As interface.

2010 - Carbon-doped GeTe Phase-Change Memory featuring remarkable RESET current reduction [Relazione in Atti di Convegno]
G., Betti Beneventi; L., Perniola; A., Fantini; D., Blachier; A., Toffoli; E., Gourvest; S., Maitrejean; V., Sousa; C., Jahan; J. F., Nodin; A., Persico; S., Loubriat; A., Roule; S., Lhostis; H., Feldis; G., Reimbold; T., Billon; B., De Salvo; Larcher, Luca; Pavan, Paolo; D., Bensahel; P., Mazoyer; R., Annunziata; F., Boulanger
abstract

In this paper we present a study of Phase-Change non-volatile Memory (PCM) devices integrating carbon-doped GeTe as chalcogenide material. Carbon-doped GeTe, named GeTeC, remarkably lowers the RESET current and features very good data retention properties as well. In particular, GeTe PCM with 10% carbon inclusions (named GeTeC10%) yields about 30% of RESET current reduction with respect to pure GeTe and GST. Furthermore, our GeTeC10% memory cells are expected to guarantee a 10-years-lifetime-temperature of about 127°C, which is one of the highest ever reported for PCM. The outstanding properties of GeTeC make this material promising for non-volatile memory technologies.

2010 - Charge loss in TANOS devices caused by Vt sensing measurements during retention [Relazione in Atti di Convegno]
H., Park; G., Bersuker; D., Gilmer; K. Y., Lim; M., Jo; H., Hwang; Padovani, Andrea; Larcher, Luca; Pavan, Paolo; W., Taylor; P. D., Kirsch
abstract

In TANOS stuctures in retention, the major decrease in theprogrammed threshold voltage is found to be caused by the Vtsensing (IdVg measurements) rather than by intrinsic charge loss(when no bias is applied). This Vt decrease can be understoodwithin the process of the temperature-activated charge transportthrough the Al2O3 blocking oxide. The charge loss can beminimized when Vt sensing time is decreased down to microseconds. Blocking oxides engineered by adding a thin SiO2 layerat the SiN/AlO interface demonstrate significant suppression of thecharge loss.

2010 - Investigation of trapping/detrapping mechanisms in Al2O3 electron/hole traps and their influence on TANOS memory operations [Relazione in Atti di Convegno]
Larcher, Luca; Padovani, Andrea; Vincenzo della, Marca; Pavan, Paolo; Bertacchini, Alessandro
abstract

The purpose of this work is to investigate the physics of electron/hole trapping/detrapping mechanisms in Al2O3. Combining I-V and C-V measurements with a physical model we derive the energy levels of electron/hole traps and the location of electron/hole charge. The influence of electron/hole alumina traps on TANOS operations and reliability is investigated.

2010 - On Carbon doping to improve GeTe-based Phase-Change Memory data retention at high temperature [Relazione in Atti di Convegno]
G., Betti Beneventi; E., Gourvestzk; A., Fantini; L., Perniola; V., Sousa; S., Maitrejean; J. C., Bastien; A., Bastard; A., Fargeix; B., Hyot; C., Jahan; J. F., Nodin; A., Persico; D., Blachier; A., Toffoli; S., Loubriat; A., Roule; S., Lhostis; H., Feldis; G., Reimbold; T., Billon; B., De Salvo; Larcher, Luca; Pavan, Paolo; D., Bensahel; P., Mazoyer; R., Annunziata; F., Boulanger
abstract

This paper investigates material and electrical propertiesof a new chalcogenide alloy for Phase-Change Memories(PCM): Carbon-doped GeTe (named GeTeC). First, severalphysico-chemical, optical and electrical analyses have beenperformed on full-sheet chalcogenide depositions in order tounderstand the intrinsic GeTeC phase-change behavior, andto characterize structure and composition of amorphous andcrystalline states. Then, GeTeC with two different Carbon doping(4% and 10%) has been integrated in pillar-type analytical PCMcells. Physico-chemical and electrical data indicate that GeTeC ischaracterized by a much more stable amorphous phase comparedto undoped GeTe. Thus, GeTeC offers a slower programmingspeed versus GeTe, but an improved data retention at hightemperature. Finally, we argue that GeTeC alloy is a promisingcandidate for future developments of PCM technologies forembedded applications.

2010 - Role of Holes and Electrons During Erase of TANOS Memories: Evidences for Dipole Formation and its Impact on Reliability [Relazione in Atti di Convegno]
Vandelli, Luca; Padovani, Andrea; Larcher, Luca; Antonio, Arreghini; Geert Van den, Bosch; Malgorzata, Jurczak; Jan Van, Houdt; Vincenzo Della, Marca; Pavan, Paolo
abstract

The systematic investigation of the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations is reported for the first time. We determined a dominance of electrons back-tunneling in the first part of the transient, and dominance of holes in the second part. Good agreement is reached between experimental and simulated data. In addition we demonstrate for the first time the formation of a vertical charge dipole in TANOS devices, whose polarity depends on the P/E operation sequence. This dipole severely affects the program and erase performances and the retention of mild programmed and erased states, which is a concern especially for multilevel applications.

2010 - SET switching effects on PCM endurance [Relazione in Atti di Convegno]
V., Della Marca; F., Carboni; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper we report results on PCM endurance failure characterization. We show that endurance failure is related to SET pulse features and we analyze and model SET operation to obtain a better understanding and improve endurance performance. Results give interesting insights on the crystallization process of GST material. SET obeys to a constant energy law. Fast SET pulses require high power; slow SET pulses can be implemented in low power applications. Results may be used for optimized SET/RESET operation to achieve better endurance.

2010 - Temperature Effects on Metal-Alumina-Nitride-Oxide-Silicon Memory Operations [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; D., Heh; G., Bersuker; V., Dellamarca; Pavan, Paolo
abstract

We present a detailed investigation of temperature effects on the operation of TaN/Al2O3 / Si3N4 /SiO2 / Si (TANOS) memory devices. We show that not only retention but also program and erase operations are affected significantly by temperature. Using a large set of experimental data and simulations on a variety of TANOS stacks, we show that the temperature dependence of TANOS program and erase operations can be explained by accounting for that the alumina dielectric constant increases by 20%–25% over a 125 K temperature range.

2009 - A technique to extract high-k IPD stack layer thicknesses from C-V measurements [Articolo su rivista]
Larcher, Luca; Pavan, Paolo; Padovani, Andrea; G., Ghidini
abstract

We propose in this letter a simple technique based on C-V measurements which allows to estimate the thicknesses of SiOX and high-k layers of IPD stacks. We apply this technique to IPD Al2O3-based stacks for floating gate memory applications, finding a good agreement with TEM measurements. In addition, simulation results are provided to demonstrate the correctness of the basic assumption of this technique.

2009 - Analytical model for low-frequency noise in amorphous chalcogenide-based phase-change memory devices [Articolo su rivista]
G., Betti Beneventi; A., Calderoni; P., Fantini; Larcher, Luca; Pavan, Paolo
abstract

Low-frequency noise has been experimentally characterized in the disordered insulating phase of chalcogenide-based phase-change memory (PCM) devices. An analytical model of noise based on the two-level systems (TLS) theory has been developed. In this framework we suggest that the origin of the 1/fγ noise in the conductivity of amorphous chalcogenides has to be ascribed to the TLS-induced fluctuations of the mean trap energy in the material. The model allows to quantitatively account for noise magnitude dependence on both voltage and temperature in the readout region of the memory device. Besides, our equations well describe the noise behavior as a function of the drift phenomenon, coherently with existing structural relaxation theories. Measurements and model results show that the noise-to-signal ratio (N/S) in the readout region of the cell is constant with respect to bias; hence there is no particular readout voltage that minimizes N/S. Furthermore, the analysis of noise data with cell scaling confirms that noise in PCMs is mainly due to the bulk properties of the chalcogenide employed rather than to interfacial effects.

2009 - Photovoltaic scavenging systems: Modeling and optimization [Articolo su rivista]
Brunelli, D.; Dondi, Denis; Bertacchini, Alessandro; Larcher, Luca; Pavan, Paolo; Benini, L.
abstract

The interest in embedded portable systems and wireless sensor networks (WSNs) that scavenge energyfrom the environment has been increasing over the last years. Thanks to the progress in the design oflow-power circuits, such devices consume less and less power and are promising candidates to performcontinued operation by the use of renewable energy sources. The adoption of maximum power pointtracking (MPPT) techniques in photovoltaic scavengers increases the energy harvesting efficiency andleads to several benefits such as the possibility to shrink the size of photovoltaic modules and energyreservoirs. Unfortunately, the optimization of this process under non-stationary light conditions is still akey design challenge and the development of a photovoltaic harvester has to be preceded by extensivesimulations. We propose a detailed model of the solar cell that predicts the instantaneous powercollected by the panel and improves the simulation of harvester systems. Furthermore, the paperfocuses on a methodology for optimizing the design of MPPT solar harvesters for self-poweredembedded systems and presents improvements in the circuit architecture with respect to our previousimplementation. Experimental results show that the proposed design guidelines allow to incrementglobal efficiency and to reduce the power consumption of the scavenger.

2008 - A Solar Energy Harvesting Circuit for Low Power Applications [Relazione in Atti di Convegno]
Dondi, Denis; Bertacchini, Alessandro; Larcher, Luca; Pavan, Paolo; D., Brunelli; L., Benini
abstract

In this paper we present a solar energy harvesting circuit for low-power applications describing circuit architecture and guidelines for an optimal design. We evaluate the performance of two implemented prototypes intended to power a wireless embedded system under different light intensities and different switching frequencies. Measurements show that higher switching frequencies allow reaching the maximum efficiency (90%) at higher light intensities, whereas lower operating frequencies perform better under lower irradiance. Experimental results show that circuit optimization depends on light conditions and the proposed solar energy harvester can autonomously supply the nodes of a wireless sensor network WSN.

2008 - Characterization and modelling of low-frequency noise in PCM devices [Relazione in Atti di Convegno]
P., Fantini; G., Betti Beneventi; A., Calderoni; Larcher, Luca; Pavan, Paolo; F., Pellizzer
abstract

Low-frequency noise in PCM devices is experimentally investigated providing a new physical model for the amorphous GST (Ge2Sb2Te5) material. Noise intensity is characterized and modelled as a function of bias, temperature and size. Findings from 1/f noise analysis are used to understand the drift mechanism of the amorphous state resistance.

2008 - Feasibility of SIO2/Al2O3 tunnel dielectric for future Flash memories generations [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; S., Verma; Pavan, Paolo; P., Majhi; P., Kapur; K., Parat; G., Bersuker; K., Saraswat
abstract

In this paper, we investigate the feasibility of SiO2/Al2O3 stack tunnel dielectric for future Flash memory generations using statistical leakage current simulations. We show that the statistical Monte Carlo (MC) simulator we employed reproduces accurately leakage currents measured on SiO2/Al2O3 dielectric capacitors. Exploiting its statistical capabilities, we calculate leakage current distributions in Flash memory retention conditions. We show that the high defectiveness of AI2O3 stacks strongly reduces the potential improvement of Flash retention due to the introduction of AI2O3 tunnel dielectric.

2008 - Hole Distributions in Erased NROM Devices: profiling method and effects on reliability [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

The NROM-cell concept has been introduced as a promising technology to replace Flash nonvolatile memory devices also in embedded products, owing to its intrinsic 2-b/cell operation and better endurance. However, the presence of physically sepa- rated electron and hole distributions generated by program and erase operations is reported to be one of the main causes of the device’s retention degradation. Therefore, a deep knowledge of the features and evolution of the nitride-storage charge is crucial for reliability, cell optimization, future scalability, and multilevel oper- ation. In this scenario, the purpose of this paper is twofold, which is as follows: 1) to introduce a combined simulative experimental method allowing profiling hole distribution in devices erased with different bias conditions and 2) to monitor through this technique the evolution of the nitride charge with cycling, correlating it to the degradation of memory reliability after cycling.

2008 - Modeling NAND Flash Memories for IC Design [Articolo su rivista]
Larcher, Luca; Padovani, Andrea; Pavan, Paolo; P., Fantini; A., Calderoni; A., Mauri; A., Benvenuti
abstract

In this letter, we present a compact model of NAND Flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simula- tion of NAND Flash memories with a limited computational effort, taking into account capacitive coupling effects which will become extremely important in future technology generations. This model is a very valuable tool for IC designers to optimize NVM circuits, particularly in multilevel applications.

2008 - On the RESET-SET transition in Phase Change Memories [Relazione in Atti di Convegno]
G., Puzzilli; F., Irrera; Padovani, Andrea; Pavan, Paolo; Larcher, Luca; A., Arya; DELLA MARCA, Vincenzo; A., Pirovano
abstract

We characterize SET operation in Phase Change Memories. A measurement procedure aiming to investigate resistance transition from amorphous to crystalline states is shown. Results give interesting insights on the crystallization process of GST material and a simple model is introduced. Crystallization process obeys to a constant energy law. Fast SET pulses require high power; slow SET pulses can be implemented in low power applications. Results may be used for an optimized design of memory cell operating conditions.

2008 - Performance Analysis of Solar Energy Harvesting Circuits for Autonomous Sensors [Relazione in Atti di Convegno]
Bertacchini, Alessandro; D., Dondi; Larcher, Luca; Pavan, Paolo
abstract

In this paper we present two different energy harvesting circuits for solar powered autonomous sensors.Both circuits are able to supply several types of sensor nodes. Performance of these circuits under different light conditions and different loads have been evaluated by experimental results conducted on implemented prototypes.Moreover, starting from the estimated working conditions of the sensor in terms of power requirements and light irradiance, the comparison between these circuits provides useful insights to help a designer in choosing of the optimal harvesting implementation.

2008 - Solar Energy Harvesting: applicazioni a bassa potenza [Altro]
Dondi, Denis; Bertacchini, Alessandro; Larcher, Luca; Pavan, Paolo; D. Brunelli e. L., Benini
abstract

Negli ultimi anni si sono sempre più utilizzate reti wireless a elevata velocità per scambiare dati su larga scala con centinaia e migliaia di nodi. I nodi di queste reti sono dei sistemi embedded, che devono essere in grado di connettersi utilizzando solo la quantità di energia fornita dalle batterie. Proprio questo è uno tra i maggiori limiti al loro funzionamento, dato che tali batterie sono in grado di alimentare questi sistemi solo per poco tempo e non continuativamente. Per questo, l’obiettivo dei recenti lavori di ricerca sia aziendale che accademico è quello di ridurre la dissipazione di potenza per aumentare la vita operativa dei nodi. In questo senso, sono state studiate architetture a bassissimo consumo di potenza e applicazioni che necessitano di bassissimo duty cycle di alimentazione. Sfortunatamente, queste tecniche non sono adatte per le applicazioni con requisiti più severi, come, ad esempio, quelle che richiedono elaborazioni di dati intensive e trasmissione di dati a una distanza e velocità superiori. Inoltre, più di recente, la ricerca scientifica sta studiando la possibilità di estrarre l’energia necessaria al funzionamento dei nodi della rete di sensori wireless da fonti alternative, ad esempio sotto forma di luce solare, vento o vibrazioni. Questo ha spinto i ricercatori a progettare sistemi di energy harvesting. L’energy harvesting non è una novità, tuttavia, mediante una metodologia efficace di progetto, la realizzazione e l’integrazione di energy harvester efficienti nei moderni sistemi embedded rimane tuttora un argomento molto stimolante. In questo scenario, questo articolo presenta un sistema di harvesting da energia solare progettato per alimentare sistemi embedded wireless a bassa potenza. Saranno analizzate l’efficienza del circuito realizzato per valori realistici di duty cycle e l’intensità luminosa del sensore. L’analisi dimostra che la scelta migliore per la configurazione operativa del sistema di energy harvesting non è unica. In particolare, una configurazione con dispositivi a bassissimo consumo di potenza (ULP) è più efficiente in condizioni di bassa intensità luminosa, mentre architetture ad alta frequenza sono ideali in condizioni di luminosità elevata.

2008 - Solar harvesting per reti di sensori wireless [Altro]
Bertacchini, Alessandro; Dondi, Denis; Larcher, Luca; Pavan, Paolo; D., Brunelli; L., Benini
abstract

Lo sviluppo di sistemi ad alimentazione perpetua, in grado di evitare la frequente sostituzione e/o ricarica delle batterie, è uno degli obiettivi di ricerca più importanti nella progettazione di sistemi embedded distribuiti e delle reti wireless di sensori. Nonostante i progressi tecnologici nella progettazione di dispositivi low-power, che possono contribuire a prolungare la durata delle batterie, la ridotta capacità degli accumulatori di energia (batterie, supercapacitor, ecc.) limita severamente l’autonomia di sistemi quali le Wireless Sensor Networks (WSN). Recentemente circuiti che convertono fonti energetiche ambientali,come l'energia solare o termica, in energia elettrica si stanno diffondendo nella comunità dei progettisti di sistemi embedded e solitamente assumono il nome di energy scavenger o energy harvester. In particolare scavengerche utilizzano piccole celle solari sono stati proposti per alimentare perpetuamente le reti di sensori. Rispetto ai tradizionali sistemi fotovoltaici su larga scala (decine o centinaia di kW), che riescono agevolmente a operare nel punto di massima potenza delle celle (maximum power point - MPP), i circuiti di gestione dell’energia elettrica generata da pannelli fotovoltaici di piccole dimensioni devono affrontare problemi aggiuntivi: (a) una ridotta quantità di energia dovuta alla dimensione delle celle; (b) la realizzazione di circuiti efficienti in grado di operare nel punto di massima potenza (MPP) di norma richiede un’alta percentuale dell’energia fornita dalla cella stessa (riducendo in pratica la potenza disponibile al sistema);(c) è presente un’interazione sostanziale fra circuiti di conversione e immagazzinamento dell’energia e i dispositivi alimentati. La progettazione deve quindi essere supportata da simulazioni, in particolare quando l’efficienza della conversione deve essere ottimizzata per basse intensità di radiazione solare. La definizione di un flusso di progettazione chiaro è perciò fondamentale per lo sviluppo di soluzioni circuitali con buone prestazioni. Simulazioni circuitali dell’intero sistema elettronico di gestione dell’energia generata dai pannelli fotovoltaici sono tipicamente disponibili per sistemi fotovoltaici a larga scala, ma si rendono fondamentali e necessarie per l’efficienza di reti di sensori wireless e sistemi low-power. Per ottenere simulazioni affidabili, è opportuno sviluppare modelli compatti e accurati e la validazione di un modello delle caratteristiche I-V non lineari dei moduli PV diventano cruciali per la progettazione dei sistemi di energy harvesting efficienti.

2008 - Statistical modeling of leakage currents through SiO2/high- κ dielectrics stacks for non-volatile memory applications [Relazione in Atti di Convegno]
Padovani, A.; Larcher, L.; Verma, S.; Pavan, P.; Majhi, P.; Kapur, P.; Parat, K.; Bersuker, G.; Saraswat, K.
abstract

We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-kappa dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-kappapsilas traps on leakage current distribution for flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-kappa tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-kappa tunnel stacks and to improve technology reliability issues related to flash memory applications.

2007 - A Wireless Wearable Embedded System for Logistics Based On IEEE 802.15.4. [Relazione in Atti di Convegno]
Bonizzi, F; Sedoni, L; Sganzerla, D; Manzoli, U; Pavan, Paolo
abstract

In this paper we present the new prototype of a portable appliance to be used for logistic operations in production warehouses. It is based on a novel and innovative wireless embedded system able to read products codes; it can also guide users through the different phases of warehouse's everyday life; the system can wirelessly transfer data, service and control/command messages to and from its coupled system server. Retail markets, pharmacies, transport and logistic activities are preferred application environments. From intensive picking to packing, from load of goods from lines to lists and warehouse checks, this system enables the user to work more efficiently and ergonomically.

2007 - A wearable IEEE 802.15.4 system for logistics scenarios [Relazione in Atti di Convegno]
Bonizzi, F; Sedoni, L; Sganzerla, D; Manzoli, U; Pavan, Paolo
abstract

We present a novel and innovative wireless embedded system for logistic applications: it is a prototype of a portable appliance to manage operations in production activity. The system is based on a wearable device which is able to read products codes and allows the system to guide users through the different phases of warehouse's everyday life; by means of IEEE 802.15.4 standard – on the ISM 2.4 GHz band – the system can wirelessly transfer data, service and control messages and commands to and from its coupled management server. The system is addressed to retail markets, pharmacies, porterage and logistic activities and it allows the user to work more efficiently and with a mobile terminal that is more ergonomic: from intensive picking to packing, from load of goods from lines to lists and warehouse checks.

2007 - Dielectric Reliability for Future Logic and Non-Volatile Memory Applications: a Statistical Simulation Analysis Approach [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; A., Chimenton; Pavan, Paolo; P., Olivo
abstract

In this paper, we present a physically-based Monte-Carlo (MC) model reproducing the leakage current flowing across typical dielectric layers (SiO2, high-k) used in ULSI technologies. Simulations will be shown to predict accurately currents measured on MOSFETs, large area MOS capacitor, and tunnel oxides of Flash memories after electrical and radiation stresses. Statistical aspects related to leakage current and threshold voltage are reproduced correctly, allowing worst case corner prediction, necessary to assess dielectric damaging effects on logic circuits and non-volatile memory operation.

2007 - EmbTrack: A Wearable IEEE 802.15.4 Tracking System for Logistics [Relazione in Atti di Convegno]
Bonizzi, F; Sedoni, L; Sganzerla, D; Manzoli, U; Pavan, Paolo
abstract

We present an innovative wireless embedded system for logistic applications: it is a prototype of a portable appliance to manage operations in production activity. The system is based on a wearable device which is able to read products codes and allows the system to guide users through the different phases of warehouse's everyday life; by means of wireless IEEE 802.15.4 standard – on the ISM 2.4 GHz band – the system can transfer data, service and control messages and commands to and from its coupled management server.Moreover by an ad-hoc procedure based on a Weighted Minimum Mean Square Error (W-MMSE) localization algorithm, the system is able to localize users within a typical logistic scenario. The system is addressed to retail markets, pharmacies, porterage and logistic activities thus allowing the user to work more efficiently and employing mobile a more ergonomic terminal: from intensive picking to packing, from load of goods from lines to lists and warehouse checks.

2007 - Hole Distributions in NROM Devices: Profiling Technique and Correlation to Memory Retention [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

In this work, we presented a new technique to profile hole distribution in NROM devices. The evolution of the nitride charge in cycled cells was monitored. The key role played by holes in NROM retention degradation was identified. Electron injection far from the junction and VT drift in erased NROM cells are successfully explained.

2007 - ID-VGS Based Tools to Profile Charge Distributions on NROMTM Memory Devices [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo; L., Avital; I., Bloom; B., Eitan
abstract

The NROM cell concept has been introduced as a promising technology to replace Flash non-volatile memory devices also in embedded products, thanks to its intrinsic two-bits/cell operation and better endurance. However, the presence of physically separated electron and hole distributions generated by program and erase operations is reported to be one of the main causes of device’s retention degradation. Therefore, a deep knowledge of the features and evolution of the nitride storage charge is crucial for reliability, cell optimization, future scalability and multi-level operation. In this scenario, the purpose of this paper is twofold: 1) to introduce a combined simulative-experimental method allowing profiling hole distribution in devices erased with different bias conditions; 2) to monitor through this technique the evolution of the nitride charge with cycling, correlating it to the degradation of memory reliability after cycling.

2007 - Modeling NAND Flash memories for circuit simulations [Relazione in Atti di Convegno]
Larcher, Luca; Padovani, Andrea; I., Rimmaudo; Pavan, Paolo; A., Calderoni; G., Molteni; F., Gattel; P., Fantini
abstract

In this paper, we will present the basic structure and the parameter extraction procedure for a compact model of a NAND Flash memory string working in Spice-like circuit simulators. To the author knowledge, this is the first Spice-like model of a NAND Flash memory string. This model is modular and simple to be implemented. It will allow accurately reproducing both DC and transient behavior of NAND Flash memories without increasing computational effort, thus becoming an indispensable tool for designers to optimize circuits especially in multi-level applications.

2007 - Monte-Carlo Simulations of Flash Memory Array Retention [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; A., Chimenton; Pavan, Paolo
abstract

One of the major scalability limitations of flash memories is anomalous SILC, which strongly endangers device reliability and data retention. Therefore, an accurate evaluation of SILC statistics on large arrays is crucial for reliability predictions and new Flash technology development. In the last years, oxide leakage currents were deeply investigated and modeled, neglecting SILC statistics and effects on large Flash arrays. More recently, analytical models relating Flash statistical threshold voltage (VT) distributions to defect statistics and leakage current were proposed. However, these models rely on several simplifying assumptions such as the equivalent cell concept and an uniform defect population. Still, these models do not account for the initial VT distribution and neglect the role played by trap energy and effective field. In this scenario, the purpose of this paper is to present a Monte-Carlo (MC) simulator reproducing flash VT distribution, which overcomes the above model limitations. We will show that this model can be used to 1) investigate effects of defect features and technology parameters on VT distribution, and 2) analyze the impact of temperature and voltage accelerated stresses on final VT distribution.

2007 - Photovoltaic Cell Modeling for Solar Energy Powered Sensor Networks [Relazione in Atti di Convegno]
Dondi, Denis; D., Brunelli; L., Benini; Pavan, Paolo; Bertacchini, Alessandro; Larcher, Luca
abstract

Photovoltaic scavenging circuits have been presentedto reduce installation and maintenance costs of wirelesssensor networks. When small-size photovoltaic modules areadopted, optimizing the efficiency of the harvesting process andtracking theMaximum Power Point (MPP) becomes very difficult,and the development of a photovoltaic harvester has to bepreceded by extensive simulations. The paper focuses on thedefinition of the model for a small PV cell allowing the simulationof harvester systems. The model is validated on a case study ofMPPT circuit for sensor networks.

2006 - Force Feedback in Steer-by-Wire Systems: Architecture and Experimental Results [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Tamagnini, Luca; Pavan, Paolo
abstract

In this paper a preliminary architecture of a force-feedback subsystem in steer-by-wire (SBW) systems is proposed. In SBW applications, a force feedback control is needed to recreate on a steering wheel (or another man-machine interface) a drive feeling like the one produced by a traditional mechanical steering system. In this case a brushless motor is used as force feedback actuator. To validate the proposed architecture we adopted a Hardware-in-the-Loop (HIL) approach. HIL is a powerful development tool. In particular, a dynamic model of the vehicle is implemented in virtual hardware. The model is needed to evaluate the realized hardware (ECU and inverter needed to operate the motor) and to validate the force feedback control algorithms before the real implementation of the complete SBW system.Experimental results show as the realized ECU and the implemented control algorithm based on a field oriented control technique are correct and particularly suitable for steer-by-wire applications.

2006 - Hardware-in-the-Loop Approach for Redundant Brushless Motor Control System [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Pavan, Paolo; Tamagnini, Luca; M., Mistrorigo; M., Morandi
abstract

Brushless motors can be used in a very large range of industrial applications, including force feedback actuators in steer-by-wire systems. Due to the safety critical requirements of this kind of applications, a fault tolerant architecture is needed and it is implemented here using a Hardware-in-the-Loop (HIL) approach.To obtain a reliable control system a classic Triple Modular Redundancy (TMR) architecture has been designed. The very same basic principles to control the motor have been implemented exploiting three different hardware platforms (8-bit, 16-bit and hybrid microcontrollers). All these three hardware modules execute the control algorithm and it will be the voter of the TMR architecture to determine the effective signals (PWM signals) needed to control the motor.This means that redundancy is not limited to the determination of the position of the drive shaft of the motor, but extended to the entire electronic control of the brushless motor

2006 - Profiling charge distribution in NROM devices [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

NROM memory cells are proposed as one of the most promising non-volatile memories. Issues on scaling and endurance have risen due to the presence of both electrons and holes, for the control of their relative position and spread in the charge trapping material. Therefore, a deeper analysis of the injected-charge distribution region is very important for program/erase bias optimization, reliability prediction and future scaling. In this paper, we introduce and discuss two tools, based on subthreshold slope and temperature effects, able to correctly estimate program charge distribution features from simple ID - VGS measurements

2006 - Temperature Monitor: a New Tool to Profile Charge Distribution in NROMTM Memory Devices [Relazione in Atti di Convegno]
L., Avital; Padovani, Andrea; Larcher, Luca; I., Bloom; R., Arie; Pavan, Paolo; B., Eitan
abstract

NROM memory cells are proposed as one of the most promising non-volatile memories. Issues on scaling and endurance have risen due to the presence of both electrons and holes for the control of their relative position and spread in the charge trapping material. In this paper, we present a new characterization tool able to sense charge distribution features in different program/erase conditions that can be efficiently used for program/erase bias optimization and reliability predictions. This new tool exploits temperature effects on ID-VGS current measurements

2006 - W2TS: A novel IEEE 802.11 multi-hop mesh network for tracking systems [Relazione in Atti di Convegno]
D., Dondi; F., Bonizzi; U., Manzoli; Pavan, Paolo
abstract

We present a novel and innovative wireless tracking system for service vehicles in areas where the vehicles position could affect people security and operational functionalities; a communication system to acquire and transmit mobile agents GPS position data to an Area Control Station has been studied and implemented. As mobile agents (vehicles) are free to moveover the operational area, the target of the system is to provide a reliable tracking service employing a wireless backbone, comprised of fixed stations. The novel solution proposed here will manage the communication between mobile agents and the backbone network with a specific AODV routing protocol, and the static backbone network with a co-existent different customizedOLSR routing protocol.

2006 - XBW s.r.l. - Mechatronic Solutions [Spin Off]
Pavan, Paolo; Bertacchini, Alessandro; L., Tamagnini; M., Mistrorigo; M., Morandi
abstract

2005 - Control of Brushless Motor with Hybrid Redundancy for Force Feedback in Steer-by-Wire Applications [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Tamagnini, Luca; L., Fergnani; Pavan, Paolo
abstract

In this paper we propose a Hardware-in-the-Loop (HIL) approach to implement a preliminary architecture for force-feedback control in steer-by-wire (SBW) applications. A brushless motor is used as force feedback actuator. The determination of the position of the rotor plays a key role in the control algorithm.To obtain a reliable rotor position a hybrid redundancy has been implemented. The position signals of the encoder integrated on the motor are computed in three different ways: using a 8-bit microcontroller, a 16-bit microcontroller, and, last, using a FPGA. A virtual hardware platform operates as voter. The position estimated by the voter is used by the 16-bit platform to generate the PWM signals needed to control the motor.The voter executes a simple self diagnostic process, too and in case of failure in more than one module performs a reconfigurations of the system and the position estimated by a fourth back-up module is used by the 16-bit microcontroller to implement the motor control algorithm.In particular, the results of Hardware-in-the-Loop experiments show as using a redundant architecture like the one proposed in this paper, it is possible to control the motor in order to recreate on a steering wheel (directly connected to the motor) a drive feeling like the one produced by a traditional steering system also in case of failure in one, or more than one module, of the system.

2005 - Control of brushless DC motor with static redundancy for force-feedback in steer-by-wire applications [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Pavan, Paolo; Tamagnini, Luca; M., Mistrorigo
abstract

In this paper we propose a Hardware-in-the-Loop (HIL) approach to implement a preliminary architecture for force-feedback control in steer-by-wire (SBW) applications. A brushless DC motor (BLDC) is used as force feedback actuator. The determination of the position of the BLDC rotor plays a key role in the control algorithm.To obtain a reliable rotor position a classic triple static redundancy (TMR) is implemented. The position signals from the encoder integrated on the motor are computed in three different ways: using a 8-bit microcontroller, a 16-bit microcontroller, and, last, using the software module integrated in a virtual hardware development tool. The virtual hardware platform operates as voter, too. The position is the output of the voting algorithm and it is sent to the 16-bit platform that controls the motor and provides the correct output PWM signals.The communication between virtual hardware and real hardware uses CAN bus. The bus is monitored by a dedicated development tool. Steer-by-wire is a safety critical application and therefore requires time-triggered protocols. In this preliminary architecture a dedicated network has been implemented and therefore the disadvantages of the event-triggered protocol are considerably reduced.Experiments at different baudrates confirm that the voting algorithm produces correct results also in case of failure in one of the modules of the TMR architecture and it is not conditioned by bus loads. This means that the torque control algorithm of the BLDC motor can generate on the steering wheel (directly connected to the motor) a drive feeling like the one produced by a traditional steering system also in this fail-mode.

2005 - Design of a high-performance optical system for angular position measurement: optical and electronic strategies for uncertainty reduction [Articolo su rivista]
Rovati, Luigi; M., Bonaiuti; Pavan, Paolo
abstract

A high-performance optical system to reduce measuring errors and uncertainty in angular encoders is presented. We propose a novel reading optical head, which exploits a lens system to improve the speed of the beam crossing the photodelector and a quadrant photodiode to perform a zero-crossover acquisition of the timing information.

2005 - Flash memories for SoC: an overview on system constraints and technology issues [Relazione in Atti di Convegno]
Larcher, Luca; Pavan, Paolo; A., Maurelli
abstract

Flash memories are today one of the fundamental building blocks in modern electronic systems. Their performance (speed, consumption, alterability, nonvolatility) and the increasing importance of system reconfigurability push for flash memory integration in SoC. Unfortunately, flash integration introduces new issues both at system and at circuit/technology levels that need to be deeply investigated. From the system point of view, several aspects are involved in the choice of the flash memory type to be integrated in SoC: the most important ones, depending on the specific applications and requirements (cost, power consumption, reliability and performance requirements), are illustrated. Also circuit-technology issues specific to flash integration with high-speed logic are discussed in depth by analyzing the real case of an embedded 1-T NOR flash memory.

2005 - Sperimentando con CANbus - Controllo di un motore brushless con ridondandza statica per applicazioni di force-feedback in sistemi steer-by-wire [Altro]
Bertacchini, Alessandro; L., Tamagnini; M., Mistrorigo; Pavan, Paolo
abstract

In questo articolo viene proposto un approccio Hardware-in-the-Loop (HIL) per la realizzazione di una architettura preliminare di controllo di force feedback in applicazioni Steer-by-Wire (SBW). Come attuatore è stato scelto un motore brushless. La determinazione della posizione dell’albero motore gioca un ruolo chiave nell’algoritmo di controllo.Per ottenere una posizione affidabile dell’albero motore si è scelto di implementare una classica ridondanza statica tripla (TMR – Triple Modular Redundancy). I segnali provenienti dall’encoder integrato nel motore sono stati elaborati sfruttando tre differenti piattaforme HW: la prima basata su microcontrollore a 8-bit, la seconda basata su microcontrollore a 16-bit mentre la terza sfrutta un modulo software integrato nel tool di sviluppo utilizzato come HW virtuale. La piattaforma di HW virtuale è utilizzata anche come voter. La posizione effettiva dell’albero motore, risultato dell’ algoritmo di voting, è inviata via bus CAN alla piattaforma a 16-bit che implementa l’algoritmo di controllo del motore e genera i segnali PWM necessari all’alimentazione del motore.La comunicazione tra HW virtuale e reale avviene attraverso bus CAN. Esperimenti condotti a diverse baudrates confermano la validità dell’algoritmo di voting implementato, che produce risultati corretti anche in caso di guasto in uno dei moduli dell’architettura TMR e non è influenzato da condizioni di alto carico del bus di comunicazione.

2005 - Statistical Simulations of Oxide Leakage Current in MOS Transistors and Floating Gate Devices [Relazione in Atti di Convegno]
Larcher, Luca; Pavan, Paolo
abstract

The purpose of this paper is to illustrate a physically-based model allowing the statistical simulations of oxide leakage currents in MOS transistors and Floating Gate memories. This model computes the leakage current through defects randomly generated in the oxide, in case accounting for the formation of percolation paths. Furthermore, a calculation procedure has been developed to calculate the threshold voltage of FG memories from simulated oxide leakage currents in some reliability conditions, thus allowing to investigate their actual Flash data retention issues and their future trends. To this regards, it will be shown how this simulation model can be used to investigate threshold voltage shift occurring in retention conditions in FG memories after both Program/erase cycles, i.e. electrical stress and radiation exposure.

2004 - A wireless network system for low data rata and multimedia data communications on trains [Relazione in Atti di Convegno]
F., Bonizzi; U., Manzoli; Larcher, Luca; Pavan, Paolo
abstract

This paper presents a wireless network system implemented on trains which is suitable for both low and high (multimedia) data rate communication. The network system is comprised of a low rate data communication section, which provides communication services useful for system management, information transmission and train monitoring. A separate section is provided with high data rate communication capabilities, which enables multimedia infotainment applications. The proposed network system is based on wireless technologies in the ISM band, i.e. Bluetooth and Wi-Fi, exploiting their characteristics to optimize the performance of the two sections. Every network node includes an embedded system required to manage the wireless network interface. The embedded system hardware architecture has been developed “ad-hoc”, as well as software procedures and algorithms needed for communication system management.

2004 - An embedded system for wireless data communications on trains [Relazione in Atti di Convegno]
F., Bonizzi; U., MANZOLI U; Larcher, Luca; Pavan, Paolo; D., Liziero
abstract

This paper presents a new wireless networksy.wm implemented on trains. This nehvork system providescommunicatio~i sewices ,for data tran.sfir and systemmanugement roefiil Jbr infornrotion tran.~mi.ssiona nd trainmonitoring. It i . h~u sed on the Bliietrioth technolos. ~vhichi . ~ iised to inte~connecf the varions train cars to thelocomotive. Every nehvork node is composed hy a powe~firlembedded sjsrem reqriired to control the Blnrtooth nehvorkinrerfirce. We developed hoth hardware architecture andsojtx.are desigti of this emhedded sy.stem. which allows to'achieve a,f& mid @cient implementation of'the protocolsand a1gorith;is drsigned for the commiinication systemmanagement

2004 - Floating Gate devices: operation and compact modeling [Relazione in Atti di Convegno]
Larcher, Luca; Pavan, Paolo
abstract

This paper describes a possible approach to Compact Modeling of Floating Gate devices. Floating Gate devices are the basic building blocks of Semiconductor Nonvolatile Memories (EPROM, EEPROM, Flash). Among these, Flash are the most innovative and complex devices. The strategy followed developing this new model allows to cover a wide range of simulation conditions, making it very appealing for device physicists and circuit designers.

2004 - Floating gate devices: operations and compact modeling [Monografia/Trattato scientifico]
Pavan, Paolo; Larcher, Luca; A., Marmiroli
abstract

The goal of this book is twofold. First, it explains the principles and physical mechanisms of Floating Gate device operations. Second, starting from a general overview on Compact Modeling issues, it illustrates features and details of a complete Compact Model of a Floating Gate device, the building block of Flash Memories, one of the “hottest” products in the semiconductor industry. Flash Memories are one of the most innovative and complex types of high-tech, nonvolatile memories in use today [see, for example, Proceedings of the IEEE, Special Issue on: Flash Memory Technology, April 2003]. Since their introduction in the early 1990s, these products have experienced a continuous evolution from the simple first products to emulate EPROM memories, to the extreme flexibility of design application in today products. This is an enabling technology: future limits are beyond our current expectations and limited only by our imagination.In the memory arena, Flash memory is the demonstration of the pervasive use of new electronic applications in our lives. Every new application can exploit this flexible and powerful memory technology, either as a stand-alone component or integrated as the enabling feature of the whole silicon integration.Flash are not just memories, they are “complex systems on silicon”: they are challenging to design, because a wide range of knowledge in electronics is required (both digital and analog), and they are difficult to manufacture. Physics, chemistry, and other fields must be integrated; and conditions must be carefully monitored and controlled in the manufacturing process.Memories demand massive investments in R&amp;D, but they also reward with enormous potential market values. Flash memory market (considered the most important market segment among nonvolatile memories) is expected to progress at a very fast pace, and to gain the second place in the overall memory market. This is due to the optimization of cost/performance tradeoffs, and in particular to the inherent flexibility and versatility of this memory, which brings benefits in many applications.The leading application is in multimedia systems, which require memories that are increasingly larger in size, and demand ever-increasing performance characteristics. Telecommunications, computers, automotive and consumer electronics are some additional areas where these memories make possible numerous emerging applications.Moreover, the Flash memory integration is one of the irreplaceable requirements for further technological innovations, and particularly to realize the so-called system on silicon.Compact Model (CM) means an analytic model of the electrical behavior of a circuit element. Modeling is usually aimed at providing means to simulate the behavior of a device or a circuit by quantitative calculation. CM allows to highlight basic properties of a device, thus making easier the understanding and the synthesis of robust circuits. Therefore, the main intent of modeling is to forecast the behavior of a system. This holds for all integrated devices (resistors, capacitors, inductors, transistors, and also the device subject of this book: the floating gate device) and circuits. Compact Models of Floating Gate devices have the same purpose of all compact models: to be used within a program for circuit simulation. The Floating Gate transistor is the building block of a full array of memory cells and a memory chip. In a first approximation, the reading operation of a FG device, and for some cases also programming and erasing, can be considered a single-cell operation. Nevertheless, CMs are fundamental to simulate the effects of the cells not directly involved in the operation under investigation and the effects of the parasitic elements. Furthermore, they allow the simulation of the interaction with the rest of the device, and hence they are useful to check the design of the circuitry around the memory array:

2004 - Introduction to the Special Issue on Nonvolatile Memory Reliability, IEEE Transactions on Device and Materials Reliability [Curatela]
P., Cappelletti; Pavan, Paolo
abstract

This Special Issue of the IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY is intended to give a com- prehensive picture of the state-of-the-art in the field of non- volatile memories. It is an important opportunity for the NVM technical community to document their progress, reporting on recent achievements and future challenges.

2004 - On the physical mechanism of the NROM memory erase [Articolo su rivista]
Larcher, Luca; Pavan, Paolo; B., Eitan
abstract

The purpose of this paper is to investigate the physical mechanism of NROM memory erase. Three conduction mechanisms potentially responsible of NROM erase will be analyzed (tunneling and emission of electrons through both bottom and top oxide, tunneling and injection of holes over the bottom oxide barrier) by means of standard two-dimensional simulations and ad-hoc models reproducing hole and electron transport mechanisms across the oxide not included in standard device simulators. Hot-hole injection will be identified as the actual conduction mechanism of NROM erase, and two compact models capable to describe the main characteristics of NROM erase current will be developed.

2004 - Statistical simulations for flash memory reliability analysis and prediction [Articolo su rivista]
Larcher, Luca; Pavan, Paolo
abstract

In this paper, through the use of a recently proposed statistical model of stress-induced leakage current, we will investigate the reliability of actual Flash memory technologies and predict future trends. We investigate either program disturbs (namely gate and drain disturbs) and data retention of state-of-the-art Flash memory cells and use this model to correlate the induced threshold voltage shift to the typical outputs coming from oxide characterization, that are density, cross section, and energy level of defects. Physical mechanisms inducing the largest threshold voltage (V-T) degradation will be identified and explained. Furthermore, we predict the effects of tunnel oxide scaling on Flash memory data retention, giving a rule of thumb to scale the tunnel oxide while maintaining the same retention requirements.

2004 - embit s.r.l. [Spin Off]
Pavan, Paolo; F., Bonizzi
abstract

2003 - A complete model of (EPROM)-P-2 memory cells for circuit simulations [Articolo su rivista]
Pavan, Paolo; Larcher, Luca; M., Cuozzo; P., Zuliani; A., Conte
abstract

(EPROM)-P-2 memory devices are widely used in embedded applications. For an efficient design flow, a correct modeling of these memory cells in every operation condition becomes more and more important, especially due to power consumption limitations. Although (EPROM)-P-2 cells are being used for a long time, very few compact models have been developed. Here, we present a complete compact model based on an original procedure to calculate the floating gate Potential in dc conditions, without the need of any capacitive coupling coefficient. This model is designed as a modular structure, so to simplify program/erase and reliability simulations. Program/erase and leakage currents are included by means of simple voltage-controlled current sources implementing their analytical expression. It can be used to simulate memory cells both during read operation (dc conditions) and during program and erase (transient conditions) giving always very accurate results. We will show also that, provided good descriptions of degradation mechanisms, the same model can be used also for reliability simulations, predicting charge loss due to tunnel oxide degradation.

2003 - Bluetooth embedded systems for home automation [Relazione in Atti di Convegno]
F., Bonizzi; G., Finelli; F., Giva; L., Sedoni; U., Manzoli; R., Morselli; Pavan, Paolo
abstract

This paper presents a wireless home control system based on Bluetooth technology. A wireless home network, that allows to control and monitor home devices, is realized and it can be accessed also by internet. An embedded system, which enables the normal devices to be interconnected without wire, is developed, showing either hardware and software design aspects.

2003 - Bluetooth embedded systems for home automation [Capitolo/Saggio]
Bonizzi, F.; Finelli, G.; GIVA F., SEDONI L.; Manzoli, U.; Morselli, R.; Pavan, Paolo
abstract

This paper presents a wireless home control system based on Bluetooth technology. A wireless home network, that allows to control and monitor home devices, is realized and it can be accessed also by internet. An embedded system, which enables the normal devices to be interconnected without wire, is developed, showing either hardware and software design aspects.

2003 - CMOS and Interconnect Reliability - Flash Reliability/Hot Carrier Effects [Relazione in Atti di Convegno]
Pavan, P.; Owens, A.
abstract

2003 - Control Structures and Physical Requirements for Steer-By-Wire Systems [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Morselli, Riccardo; Zanasi, Roberto; Pavan, Paolo; Bertoli, A.
abstract

Starting from the dynamic model of a conventional steering system, this paper proposes some hardware-independent control structures for the implementation of a steer-by-wire system for ground vehicles. Moreover the proposed approach allows the definition of the physiscal requirements on the real implementation and it can be used as a desgin tool fore the evaluation of the dynamic behaviour of al the steer-by-wire mechatronic devices.

2003 - Energetic Approach for Steer-by-Wire in Off-highway Vehicles [Relazione in Atti di Convegno]
Morselli, Riccardo; Bertacchini, Alessandro; Reggiani, W.; Pavan, Paolo; Zanasi, Roberto
abstract

Starting from an energetic model of a traditional steering system, this paper proposes three different kinds of architecture for the implementation of a steer-by-wire system on off-highway vehicles. The force feedback and the rack hydraulic control cannot be ideal systems and this affects the overall vehicle dynamics, moreover the effects on the vehicle behavior depends on the chosen architecture. The hardware independent approach proposed in the paper drives the definition of the control requirements on the steering wheel control and on the rack control subsystems and it allows to appreciate the effects of the architecture on the implementation of a steer-by-wire system.

2003 - Statistical simulations to inspect and predict data retention and program disturbs in Flash memories [Relazione in Atti di Convegno]
Larcher, Luca; Pavan, Paolo
abstract

A new statistical model of stress-induced leakage current (SILC) is implemented and used to predict data retention and program disturbs of state-of-the-art flash memories, and to correlate oxide characterization outputs (density, cross section, energy level of defects) to flash memory reliability. Physical mechanisms inducing the largest threshold voltage (VT) degradation are explained, and tunnel oxide scaling effects on flash reliability are predicted.

2003 - Testing Steer-by-Wire Controllers for Off-Highway Vehciles by Hardware-in-the-Loop Experiments [Capitolo/Saggio]
Bertacchini, Alessandro; Morselli, Riccardo; Pavan, Paolo; Zanasi, Roberto
abstract

The control laws and the hardware architecture for the implementation of a steer-by-wire system for off-highway vehicles are proposed. This paper describes how the hardware-independent control laws for the steer-by-wire actuators have been obtained, it explains the motivations for the choice of the force feedback actuator and of the steering rod electro-hydraulic actuator and finally it presents some hardware-in-the-loop simulation results that test the electro-hydraulic rod actuator and the electronic control unit dedicated to the steering rod

2003 - Testing Steer-by-Wire Controllers for Off-Highway Vehicles by Hardware-in-the-Loop Experiments [Relazione in Atti di Convegno]
Bertacchini, Alessandro; Morselli, Riccardo; Pavan, Paolo; Zanasi, Roberto
abstract

The control laws and the hardware architecture for the implementation of a steer-by-wire system for off-highway vehicles are proposed. This paper describes how the hardware-independent control laws for the steer-by-wire actuators have been obtained, it explains the motivations for the choice of the force feedback actuator and of the steering rod electro-hydraulic actuator and finally it presents some hardware-in-the-loop simulation results that test the electro-hydraulic rod actuator and the electronic control unit dedicated to the steering rod.

2002 - A Complete Study of SILC Effects on EEPROM Reliability [Relazione in Atti di Convegno]
Larcher, Luca; S., Bertulu; Pavan, Paolo
abstract

In this paper, we investigate SILC effects on E2PROM reliability: the influence of Program/Erase bias and cycle number, of oxide thickness scaling and quality, and of storage field on retention properties of E2PROM memory cell. To accomplish this task, we use a recently proposed compact E2PROM model, extended to include SILC, thus bridging the gap between oxide quality characterization activity performed on MOS test structures, and its actual impact on E2PROM memories.

2002 - A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling [Relazione in Atti di Convegno]
Larcher, Luca; Pavan, Paolo
abstract

This paper presents for the first time a new approach to hot-carrier phenomena leading to an analytical model of both Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) currents. This model can be incorporated in Spice-like models of MOS transistors and Floating Gate (FG) devices to include hot carrier phenomena also in circuit simulations.

2002 - A complete study of SILC effects on E2PROM reliability [Relazione in Atti di Convegno]
Larcher, L.; Bertulu, S.; Pavan, P.
abstract

In this paper, we investigate SILC effects on E2PROM reliability: the influence of Program/Erase bias and cycle number, of oxide thickness scaling and quality, and of storage field on retention properties of E2PROM memory cell. To accomplish this task, we use a recently proposed compact E2PROM model, extended to include SILC, thus bridging the gap between oxide quality characterization activity performed on MOS test structures, and its actual impact on E2PROM memories.

2002 - A new compact DC model of floating gate memory cells without capacitive coupling coefficients [Articolo su rivista]
Larcher, Luca; Pavan, Paolo; S., Pietri; L., Albani; A., Marmiroli
abstract

This paper presents for the first time a new compact SPICE model of floating gate nonvolatile memory cells capable to reproduce effectively its complete dc electrical behavior in every bias conditions. This model features many advantages compared to previous ones: it is simple and easy to implement since it uses SPICE circuit elements, is scalable, and its computational time is not excessive. It is based on a new procedure that calculates the floating gate voltage without using fixed capacitive coupling coefficients, thus improving the floating gate voltage estimate that is fundamental for the correct modeling of cell operations. Moreover, this model requires only the usual parameters adopted for SPICE-like models of MOS transistors plus the floating gate-control gate capacitance, making it very attractive to industry as the same parameter extraction procedure used for MOS transistors can be directly applied. The model we propose has been validated on (EPROM)-P-2 and Flash memory cells manufactured in existing technology (0.35 mum and 0.25 mum) by STMicroelectronics.

2002 - Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells [Articolo su rivista]
Larcher, Luca; Verzellesi, Giovanni; Pavan, Paolo; Lusky, E.; Bloom, I.; Eitan, B.
abstract

The aim of this paper is to achieve a correct description of programming charge distribution in NROM memory devices. This is essential to prove device functionality and to extrapolate scaling limits of devices. To this purpose we use an inverse modeling based methodology using measurements easily performed, such as subthreshold characteristics and threshold voltage measurements. We will show a simple model of programming charge distribution that can be easily implemented in 2D TCAD simulations. Results show good agreement between measured and simulated currents under different bias conditions and for different programming levels.

2002 - NROM (TM) - a new technology for non-volatile memory products [Articolo su rivista]
I., Bloom; Pavan, Paolo; B., Eitan
abstract

NROM(TM)-is a new technology for non-volatile memories (NVMs); it offers three major improvements relative to the Floating Gate technology: one technology for all NVM products (Flash, EEPROM, ROM and Embedded), higher density (2.5F(2)/bit in Flash, where F is the feature size of the process), and simpler process with reduced number of masks without any exotic materials. The NROM(TM) cell is based on localized charge trapping above the junction edge, storing two physically separated bits per cell. Performance of new NVM NROM(TM) based products show endurance up to 100 K with retention of 10 years at 150 degreesC. (C) 2002 Elsevier Science Ltd. All rights reserved.

2002 - SILC effects on EEPROM memory cell reliability [Articolo su rivista]
Larcher, Luca; Bertulu, S.; Pavan, Paolo
abstract

In this paper, we will investigate SILC effects on the reliability of E2PROM memories. Particularly, we will analyze the influence on the retention properties of E2PROM memory devices of Program/Erase number of cycles and bias conditions, oxide thickness scaling and quality, and storage field. To accomplish this task, we will use a recently proposed compact E2PROM model, which has been extended to include SILC, thus bridging the gap between the oxide quality characterization activity performed on MOS transistors and capacitors, and the actual impact of SILC on the functioning of E2PROM memories.

2001 - A New Compact Model of Floating Gate Non-Volatile Memory Cells [Relazione in Atti di Convegno]
Larcher, Luca; Pavan, Paolo; F., Gattel; L., Albani; A., Marmiroli
abstract

This paper presents a new compact model of Floating Gate Non-Volatile Memory Cells using SPICE circuit elements. It features many advantages compared to previous models: it is simple and easy to implement, scalable, and its computational time is not critical, thus making it very attractive to industry. It is based on a new procedure that improves the floating gate voltage estimate. The parameter extraction procedure is the same of a MOS transistor.

2001 - A new compact Spice-like model of E2PROM Memory cells suitable for DC and transient simulations [Relazione in Atti di Convegno]
Larcher, Luca; Pavan, Paolo; Cuozzo, M.; Marmiroli, A.
abstract

This paper presents for the first time a new compact Spice-like model of an E2PROM memory cell suitable for both DC and transient circuit simulations. This model is based on a new Floating Gate voltage calcuation procedure that improves strongly the accuracy of the modeling of the cell. Moreover, this model features many advantages compared to the previous ones: i) it is simple to implement and scale; ii) its computational time is not critical; iii) its parameter extractin procedure is the same of a MOS transistor; iv) it can be easily upgraded tot ake into account leakage current contributions (SILC).

2001 - A new model of gate capacitance as a simple tool to extract MOS parameters [Articolo su rivista]
Larcher, Luca; Pavan, Paolo; F., Pellizzer; G., Ghidini
abstract

This paper tackles the difficult task to extract MOS parameters by a new model of the gate capacitance that takes into account both poly-Si depletion and charge quantization and includes temperature effects. A new fast and iterative procedure, based on this simplified self-consistent model, will be presented to estimate simultaneously the main MOS system parameters (oxide thickness, substrate, and poly-Si doping) and oxide held, surface potentials at the Si/SiO2 and at the poly-Si/SiO2 interfaces. Its effectiveness will be demonstrated by comparing oxide field and oxide thickness to those extracted by other methods proposed in the literature. Moreover, these methods are critically reviewed and we suggest improvements to reduce their errors, The agreement between CV simulation and experimental data is good without the need of any free parameter to improve the fitting quality for several gate and substrate materials combinations. Finally, a simple law to estimate substrate and poly-Si doping in n+/n+ MOS capacitor from CV curves is proposed.

2001 - Bias and W/L dependence of capacitive coupling coefficients in floating gate memory cells [Articolo su rivista]
Larcher, Luca; Pavan, Paolo; L., Albani; T., Ghilardi
abstract

In this paper, a complete study of capacitive coupling coefficients dependence on bias and W/L will be presented, including a review on classic methods to extract their value from electrical characterization. Capacitive coupling ratios have been usually adopted to model floating gate (FG) memory cells, in particular to deduce the value of FG potential. Now they are determined by means of a new model (recently proposed in the literature), starting from a new procedure to evaluate the FG potential. Results obtained with this new model will be compared to classic values. Particularly, their bias dependence (during write/read/erase of Flash memory cells) will be deeply investigated, thus demonstrating the limits of considering them constants, as is usually done. By analyzing their W/L dependence, we will deduce useful information on the effects of scaling and the role played by fringing capacitances. The most important methods reported in the literature to estimate the control gate and drain capacitive coupling ratios will be accurately reviewed, thus showing that such procedures are often cumbersome and inaccurate. It is worth noting that for the first time, alpha (B) and alpha (S) will be studied in detail.

2001 - Flash Memories [Relazione in Atti di Convegno]
Pavan, Paolo; Zanoni, E.
abstract

This paper provides an overview of Floating Gate technology, the architectures used in it, and the major applications in which it is found. New technologies and devices are discussed and compared to industry standard devices.

2001 - NROM – a new Non Volatile Memory Technology: from Device to Products [Relazione in Atti di Convegno]
I., Bloom; Pavan, Paolo; B., Eitan
abstract

NROM™ — a new NVM technology has recently been introduced, enabling three major improvements relative to the floating gate technology: one technology for all NVM products (Flash, EEPROM, ROM and Embedded), higher density (2.5F2 per bit in flash) and simple process with reduced number of masks without any exotic materials. The NROM™ cell is based on localized charge trapping above the junction edge, enabling physically separated two bits per cell. Performance of new NVM NROM™ based products show endurance up to 100 K with retention of 10 years at 150°C.

2000 - A new methodology for SEE testing and simulation [Relazione in Atti di Convegno]
Pietri, S.; Pavan, Paolo; Iacono, S.; Striccoli, M.
abstract

Integrated circuits for space application are tested at accelerators for their susceptibility to Single Event Effects. The high cost and the limited avaliability associated with accelerators testing suggest the development of new low cost techniques. Pulsed laser provides results that can be correlated with ion test results (despite the different physical interaction between semiconductor and ion or laser) and also temporal and spatial information of SEEs. CAD simulators are always used in design and they can be exploited at early stages of the project to accomplish a "smart test" procedure. This new testing methodology overcomes some limitations of laser testing: by coupling a laser equipment with a software simulator and CAD tools, an economic equipment for reliable SEE testing is obtained.

2000 - Degradation mechanisms in polysilicon emitter bipolar junction transistors for digital applications [Articolo su rivista]
L., Vendrame; Pavan, Paolo; G., Corva; A., Nardi; A., Neviani; E., Zanoni
abstract

This paper is a thorough overview on polysilicon bipolar junction transistors' (BJTs) reliability, with focus on transistors for digital applications, where the base-emitter junction switches from forward to reverse bias (low fields) and the base-collector junction is reverse biased at high fields. The effects of base-emitter reverse biasing are generation, charging and discharging of traps in silicon oxide or at the Si-SiO2 interface near the base-emitter junction; their understanding is essential to model transistor current gain degradation and low frequency noise increase. Failure modes and mechanisms, degradation kinetics, lifetime models and physical phenomena related to device aging will be discussed. The base-emitter junction is also stressed by high currents, which lead, for example, to electromigration phenomena. The base-collector junction degradation is mainly due to high field and impactionization effects. Reliability constraints are now an important component of a correct design methodology in deep-sub-micron integrated circuits. (C) 2000 Elsevier Science Ltd. All rights reserved.

2000 - Endurance optimization in microFlash Memory Device [Relazione in Atti di Convegno]
Aloni, E.; Gutman, M.; Roizin, Y.; Finzi, D.; Hyun, C. I.; Bloom, I.; Levy, D.; Lann, A.; Pavan, Paolo
abstract

The microFlash (NROM) concept is a 2-bit memory cell using an ONO dielectric as a storage media. To establish the capabilities and applications of the technology, endurance tests were performed on a 2Mb device. No limitation was found to cycle the device to 10,000 cycles and beyond. The microFlash process has been qualified ad implemented in production for applications requiring a limited number of program-erase cycles. The pbjective of the described work was to significantly increase the number of cycles. R&D is in progress to qualify the device for 10,000 cycles.

2000 - NROM: A novel localized trapping, 2-bit nonvolatile memory cell [Articolo su rivista]
B., Eitan; Pavan, Paolo; I., Bloom; E., Aloni; A., Frommer; D., Finzi
abstract

This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal similar to 400 electrons above a n(+)/p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection, The new read methodology is very sensitive to the location of trapped charge above the source, This single device cell has a two physical bit storage capability, The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250 degreesC, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 mum process, the area of a bit is 0.315 mum(2) and 0.188 mum(2) in 0.25 mum technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications.

1999 - Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells? [Relazione in Atti di Convegno]
Eitan, B.; Pavan, Paolo; Bloom, I.; Aloni, E.; Frommer, A.
abstract

The NROM concept is a 2 bit Flash cell based on charge storage in ONO dielectric. The cell is storing two physically separated bits with a unique method to sense the trapped charge. Programming is performed by channel hot electron injection (CHE) and erase by hot hole enhanced tunneling (HHET).For a new technology to challenge the 30 years old floating gate cells, the total solution from Cell, Array, Process, Product, and Testing has to be available. To actually "challenge" floating gate as the main Flash technology, a technology has to be in volume production. NROM technology is in initial production stage, hence we can only discuss future potential to become a true challenge to the floating gate storage concept.In this presentation, we will introduce the NROM technology. The NROM technology is compared to the Flaoting Gate Flash

1999 - Test structures and testing methods for electrostatic discharge: results of PROPHECY project [Articolo su rivista]
G., Meneghesso; E., Zanoni; A., Gerosa; Pavan, Paolo; W., Stadler; K., Esmark; X., Guggenmos
abstract

The goal of one PROPHECY subtask was to find a set of realistic test patterns for electrostatic discharge (ESD) and propose an appropriate testing method. Starting with basic test structures, a systematic analysis of the layout parameters dependence of the ESD hardness of various CMOS technologies tested according to the Human Body Model (HBM), Transmission Line Pulser (TLP) and socketed Charged Device Model (CDM) hardness has been carried out. Main emphasis has been given to the correlation between results obtained by the different test methods i.e. HEM and TLP, as well as between HEM and socketed CDM. The results obtained on the basic test structures, which are representative of an analogue technology, are compared (i) with results on optimised test patterns, which more realistically emulate the structure of the actual integrated circuits, and (ii), finally with results on several products. It is shown that the results of a careful analysis of the rest patterns can be applied to real pads, and at the end, even to products. (C) 1999 Elsevier Science Ltd. All rights reserved.

1997 - Characterization of CMOS Structures (O.6 urn process) Submitted to HBM and COM ESD Stress Tests [Relazione in Atti di Convegno]
Meneghesso, G.; Zanoni, E.; Colombo, P.; Brambilla, M.; Annunziata, R.; Pavan, P.
abstract

In this work, we present new results concerning electrostatic discharge (ESD) robustness of 0.6 um CMOS structures. Devices have been tested according to both HBM and socketed CDM (sCDM) ESD test procedures. Test structures have been submitted to a complete characterization consisting in: 1) measurement of the tum-on time of the protection structures submitted to pulses with very fast rise times; 2) ESD stress test with the HBM and sCDM models; 3) failure analysis based on emission microscopy (EMMI) and Scanning Electron Microscopy (SEM).

1997 - Characterization of CMOS structures (0.6 um process) submitted to HBM and CDM ESD stress tests [Relazione in Atti di Convegno]
G., Meneghesso; Colombo, P.; M., Brambilla; R., Annunziata; Pavan, Paolo; E., Zanoni
abstract

In this work, we present new results concerning electrostatic discharge (ESD) robustness of 0.6 um COMS structures. Devices have been tested according to both HBM and socketed CDM (sCDM) ESD test procedures. Test structures have been submitted to a complete characterization consisting in: 1) measurements of the turn-on time of the protection structures submitted to pulses with very fast rise times; 2) ESD stress tests with the HBM and sCDM models; 3) failure analysis based on emission microscopy (EMMI) and Scanning Electron Microscopy (SEM).

1997 - Effects of ESD protections on latch-up sensitivity of CMOS 4-stripe structures [Articolo su rivista]
Pavan, Paolo; Pellesi, A; Meneghesso, G; Zanoni, E.
abstract

In this paper, we present results on the influence of the turning on of ESD protection devices on the latch-up sensitivity of 0.35 mu m CMOS ICs. Moreover, we will show that layout details and circuit placement do have an influence on latch-up sensitivity, and that the presence of guard-rings greatly improves latch-up hardness.

1997 - Flash memory cells - An overview [Articolo su rivista]
Pavan, Paolo; R., Bez; P., Olivo; E., Zanoni
abstract

The aim of this paper is to give a thorough overview of Flash memory cells. Basic operations and charge-injection mechanisms that are most commonly used in actual Flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature. New cell structures and architectural solutions have been surveyed to highlight the evolution of the Flash memory technology, oriented to both reducing cell size and upgrading product functions. The subject is of extreme interest: new concepts involving new materials, structures, principles, or applications are being continuously introduced. The worldwide semiconductor memory market seems ready to accept many new applications in fields that are not specific to traditional nonvolatile memories.

1997 - HBM and CDM ESD stress test results in 0.6 μm CMOS structures [Relazione in Atti di Convegno]
G., Meneghesso; N., Grapputo; P., Colombo; M., Brambilla; Pavan, Paolo; E., Zanoni
abstract

In this work, we present new results concerning electrostatic discharge (ESD) robustness in 0.6 μm device structure. Devices have been submitted to both HBM and socketed CDM (sCDM) ESD tests. A systematic failure analysis of the stressed structures has been carried out obtaining important information on the dependence of the behaviour of these on layout parameters. Typical LDD MOSFET devices show damages which mainly consist in drain/substrate junction spiking in correspondence of the contacts: breakdown of the less deeper P implant junction (n+-substrate) can be responsible for the observed degradation. Devices having P deeper implant source and drain are more resistant than the previous ones and their failure mechanisms consist in lateral spiking. For some large structures adopting lateral bipolar transistor with or without gate polysilicon over Field oxide technology, SEM analysis and emission microscopy clearly demonstrate that early ESD failures can be attributed to a non uniform current distribution within the structures.

1997 - Hot-carrier degradation and oxide charge build-up in self-aligned etched-polysilicon npn bipolar transistors [Articolo su rivista]
Neviani, A; Pavan, Paolo; Nardi, A; Chantre, A; Vendrame, L; Zanoni, E.
abstract

The aim of this work is to present the results of several accelerated tests performed on self-aligned, etched-polysilicon, npn bipolar transistors with silicon dioxide emitter spacers, and to propose a new technique for the characterization of the electric field at the periphery (that is, at the interface between silicon and the silicon dioxide spacer) of the base-emitter junction, Tests are performed reverse-biasing at constant current the base-emitter junction (with floating collector) both in the tunneling and avalanche regime, The results are found to be in good agreement with existing degradation models, and show that degradation kinetics may depend to some extent on device layout, particularly in avalanche regime, The influence of charge injection in the oxide on degradation kinetics is also analyzed and compared to the predictions of an existing model, To this aim, a new method for estimating charge injection in the oxide is proposed; the method consists in evaluating the decrease of the electric field at the periphery of the device by measuring the temperature dependence of the tunneling component of reverse base current. The electric field behavior is then compared to the degradation dependence on stress time in the different stress regimes.

1996 - Analysis of charge storage in the base of bipolar transistors and its influence on the parasitic resistance adopting an eight terminal Kelvin test structure [Relazione in Atti di Convegno]
S., Asti; T., Cavioni; A., Neviani; Pavan, Paolo; M., Stival; L., Vendrame; E., Zanoni
abstract

A comparison between two recently proposed DC methods for the extraction of base parasitic resistance in double-base Kelvin-tapped Bipolar Junction Transistors has been performed, based on both measurement and numerical device simulation. Discrepancies in the results given by the two methods in medium and high injection regimes are shown, and the need to take into account majority carrier density modulation in the quasi-neutral base region is demonstrated. A new method for the extraction of the extrinsic component of the base resistance is proposed, based on a simple biasing scheme of the eight-terminal device.

1996 - Experimental and Monte Carlo analysis of impact-ionization in AlGaAs/GaAs HBT's [Articolo su rivista]
Canali, Claudio; Pavan, Paolo; Dicarlo, A; Lugli, P; Malik, R; Manfredi, M; Neviani, A; Vendrame, L; Zanoni, E; Zandler, G.
abstract

We present a detailed experimental and theoretical investigation of hot electron effects occurring in AlGaAs/GaAs Heterojunction Bipolar Transistors (HBT's) operating at low current densities, Electrons heated by the strong electric field at the base-collector junction give rise to impact ionization and light emission, A new general purpose weighted Monte Carlo procedure has been developed to study such effects. The importance of dead-space effects on the multiplication factor of the device is demonstrated. Good agreement is found between theory and experiment.

1996 - Hot-carrier degradation and oxide charge build-up in self-aligned etched-polysilicon npn bipolar transistors [Relazione in Atti di Convegno]
A., Neviani; Pavan, Paolo; A., Chantre; M., Stucchi; T., Tommasin; L., Vendrame; E., Zanoni
abstract

The aim of this paper is to present the results of several accelerated tests performed on self-aligned bipolar transistors with emitter spacers. We show that the problem of lifetime extrapolation is complicated by a strong dependence of degradation kinetics on device layout. We also demonstrate, by means of emission microscopy, that remarkable current crowding effects take place during accelerated testing, especially for tests performed avalanching the base-emitter junction, thus hampering the usual normalization of accelerating factors to device perimeters. A new method for evaluating charge injection in the oxide is described; the method consists in evaluating the decrease in the electric field at the periphery of the device by measuring the temperature dependence of the tunneling reverse base current component.

1996 - SPICE modelling of impact ionisation effects in silicon bipolar transistors [Articolo su rivista]
Verzellesi, Giovanni; A., Dal Fabbro; Pavan, Paolo; L., Vendrame; E., Zabotto; A., Zanini; A., Chantre; E., Zanoni
abstract

A nonlocal, energy based impact ionisation model for bipolar transistors is implemented into a general purpose circuit simulator. With respect to conventional, either empirical or electric field based, models, the proposed approach enables a more physical and accurate description of impact ionisation effects in modern, high speed bipolar transistors, where non-negligible nonstationary transport effects take place as a consequence of the strong spatial variations in the electric field at the base-collector junction. The conventional base resistance model is also modified, to take into account the base resistance dependence on bias in the presence of an impact ionisation induced reverse base current. Neglecting the influence of the reverse base current on the base resistance can result in an underestimation of the degradation of both DC and switching performance of bipolar transistors due to impact ionisation. The implemented models are validated by comparison with experimental results obtained from devices of two different technologies.

1995 - Influence of impact-ionization-induced base current reversal on bipolar transistor parameters [Articolo su rivista]
L., Vendrame; E., Zabotto; A., Dal Fabbro; A., Zanini; Verzellesi, Giovanni; E., Zanoni; A., Chantre; Pavan, Paolo
abstract

In this paper we describe a set of measurements representing a complete characterization of impact-ionization effects in bipolar transistors. We demonstrate that impact-ionization significantly influences the dependence of base resistance on current and voltages applied to the device. A dc method for the simultaneous extraction of all parasitic resistances in bipolar transistors is presented. The method can separate the influence of current-crowding on the base resistance from that of base width and conductivity modulation; the collector parasitic resistance is measured in the active region. Starting from the parameters extracted by means of these techniques, a complete and accurate circuit-model of impact-ionization effects can be defined.

1995 - Light emission microscopy as a tool for studying Si/SiO2 system degradation [Relazione in Atti di Convegno]
Pavan, Paolo; A., Chantre; G., Dal Pos; L., Vendrame; M., Stucchi; A., Neviani; E., Zanoni
abstract

Emission microscopy can be used as a tool for failure analysis and testing of Integrated Circuits. It can be used successfully to study reliability issues of Si/SiO2 systems. It is possible to locate the defect position on different devices, and to analyze the nature of the defect. Emission microscopy can be used to investigate current flows in semiconductor devices and to analyze the current distributions and its dependence on device layout.

1995 - SIMULATING RADIATION RELIABILITY WITH BERT [Articolo su rivista]
Pavan, Paolo; Tu, R; Minami, E; Lum, G; Ko, Pk; Hu, Cm
abstract

This paper describes a simulator which can be used to study the effects on circuit behaviour of two radiation phenomena: Single Event Upset (SEU) and total-dose radiation effects. The core of the device is BERT (BErkeley Reliability Tools), an IC reliability simulator. The SEU simulator uses an established methodology, but a novel choice of sensitive nodes is made, which allows a fast simulation of very large digital circuits. The total-dose simulator predicts circuit behaviour after a user-specified radiation dose using an ordinary circuit simulator, such as SPICE. Simulation results are compared to actual experimental data.

1994 - A complete radiation reliability software simulator [Articolo su rivista]
Pavan, Paolo; R., Tu; E., Minami; G., Lum; P. K., Ko; C., Hu
abstract

In this paper we describe a simulator which can be used to study the effects on circuit behavior of two radiation phenomena: Single Event Upset (SEU) and total-dose radiation effects. Using this simulator the user can predict the error rate in large circuits due to single event upset. The error rate model described here uses a well established methodology, but for the first time a different choice is made on picking up the sensitive nodes, enabling a quick prediction even for very complex circuits. The simulator predicts circuit behavior after total-dose irradiation using as inputs: the dose rate and the total dose, parameters sets that characterize the transistor response to radiation, and the circuit netlist. The total dose simulator is based on physical models of the changes in the MOSFET caused by radiation. We quantify the degradation of each MOSFET in a circuit with two parameters and determine the change in the MOSFET characteristics from pre irradiation MOSFET data. Using the "irradiated" MOSFET parameters, we can simulate circuit behavior using an ordinary circuit simulator such as SPICE. With this simulator one can study how resistant a circuit is to changes due to irradiation and design circuits to be functionally radiation "hard". The "double-kink" in the MOSFET sub threshold region due to the parasitic effect of the edge transistors can be simulated and the user is advised when leakage current is unacceptably large. The speed degradation of a ring oscillator was simulated and the results compared with actual measured data.

1994 - A physics-based, accurate SPICE model of impact-ionization effects in bipolar transistors [Relazione in Atti di Convegno]
E., Zanoni; A., Dal Fabbro; L., Vendrame; Verzellesi, Giovanni; G., Meneghesso; Pavan, Paolo; A., Chantre
abstract

A new SPICE model of the bipolar transistor including avalanche multiplication and current crowding effects is described. Impact-ionization phenomena are modelled referring to a physical description of impact-ionization coefficients, rather than to semi-empirical laws, as in previous models. We show that an accurate analysis of multiplication effects can be obtained only if the influence of impact ionization on current crowding and parasitic base resistance is included in the model and described exactly. The model also allows one to easily include high injections effects, which are important for the evaluation of breakdown voltage at high emitter current.

1994 - MEASUREMENT OF THE ELECTRON IONIZATION COEFFICIENT AT LOW ELECTRIC-FIELDS IN GAAS-BASED HETEROJUNCTION BIPOLAR-TRANSISTORS [Articolo su rivista]
Canali, Claudio; Capasso, F; Malik, R; Neviani, A; Pavan, Paolo; Tedesco, C; Zanoni, E.
abstract

Values of the electron ionization coefficient an in (100) GaAs extending the previously available data by two orders of magnitude, down to 1 cm-1, are presented. The data are directly extracted from the multiplication factor, M-1, measured in lightly doped collector n-p-n AlGaAs/GaAs Heterojunction Bipolar Transistors (HBT's). It is shown that the sensitivity of the technique is limited by the Early effect, whose influence can be reduced by driving the device at constant emitter-base bias and by using heavily doped base regions. HBT's can provide simultaneously high base doping and current gain, and represent therefore an excellent tool for these measurements.

1994 - Simulating Single Event Upset Rate with BERT [Relazione in Atti di Convegno]
Pavan, Paolo; E., Minami; R., Tu; P. K., Ko; C., Hu
abstract

The circuit level modeling of single event effects is an area of on-giong research. Using this software, users can predict the error rate due to SEU in large circuits.

1994 - Simulating single event upset error rate in large digital circuits [Relazione in Atti di Convegno]
Pavan, Paolo; E., Minami; R., Tu; P. K., Ko; C., Hu
abstract

Using this new module of Berkeley Reliability Tools (BERT), user can predict the error rate due to single event upset (SEU) in large circuits. The error rate model described here used a well established methodology, but for the first time a different choice is made on picking up the sensitive nodes, enabling a quick prediction even for large circuits.

1994 - Simulating total dose radiation effects on circuit behavior [Relazione in Atti di Convegno]
R., Tu; G., Lum; Pavan, Paolo; P. K., Ko; C., Hu
abstract

Using RAD, a new module of Berkeley Reliability Tools (BERT), as a tool, users can design circuits to be radiation hard and characterize circuit behavior in environments where radiation is present. Previous simulators could not provide circuit output waveforms after irradiation because it was difficult to simulate the effect of radiation on a circuit in operation (AC bias condition) and because radiation affected MOSFETs of different processes in different ways. We have dealt with these problems and for the first time, successfully provided "SPICE-like'' simulation results.

1993 - A compact method for measuring parasitic resistances in bipolar transistors [Relazione in Atti di Convegno]
Verzellesi, Giovanni; A., Chantre; R., Turetta; M., Cappellin; Pavan, Paolo; E., Zanoni
abstract

We present a compact experimental technique for the extraction of all parasitic series resistances of bipolar transistors, which require only few DC measurements and no special device structure. The method is based upon the fact that, due to impact ionization within the base-collector space-charge region, at a certain collector-base voltage the base current and therefore the voltage drop on the base resistance are reduced to zero.

1993 - Analysis of ESD protection networks for DMOS power transistors by means of static and time-resolved emission microscopy [Articolo su rivista]
B., Bonati; A., Canclini; M., Cavone; E., Novarini; Pavan, Paolo; R., Rivoir; M., Stucchi; E., Zanoni
abstract

Different ESD input/output protection networks, based on Zener diodes and lateral npn transistors, have been implemented with the aim of characterizing their effectiveness in protecting vertical DMOS power transistors. Failure mechanisms have been indented by means of static emission microscopy, Gated emissions microscopy, in synchronism with a voltage pulse emulating the ESD event, enables the dynamic behavior of protection structures to be analyzed, identifying lateral current crowding effects which explain the observed failure mechanism.

1993 - Electrical characterization and Reliability of double-doped drain MOS transistors compatible with an EEPROM process [Articolo su rivista]
Pavan, Paolo; L., Fratin; C., Riva; B., Vajana; E., Zanoni
abstract

Double-doped drain/source (As-P) n-MOS transistors with gate-drain and gate-source overlapping have been manu- factured within a standard CMOS EEPROM process. Owing to a decrease in the longitudinal electric field, and the enhanced control of the gate on the low doped drain region, both snap-back voltage and hot electron effects are markedly reduced, allowing reliable operation at high drain voltages at the expense of a tolerable increase in drain, source/gate capacitances. Devices have been submitted to a hot electron accelerated test at Va.,= 10 V, Vss = 5 V. The observed degradation seems to be mainly due to acceptor- type interface state creation near the drain junction.

1993 - Explanation of current crowding phenomena induced by impact ionization in advanced Si bipolar transistors by means of electrical measurements and light emission microscopy [Relazione in Atti di Convegno]
Pavan, P.; Vendrame, L.; Bigliardi, S.; Marty, A.; Chantre, A.; Zanoni, E.
abstract

This paper analyzes impact ionization phenomena in advanced polysilicon emitter bipolar transistors. Two intrinsic limitations affecting multiplication coefficient at high electric fields are discussed. Emission microscopy is adopted to directly investigate and observe current crowding effects at the basis of the first kind of instability, which takes place when the device is driven at constant emitter current IE. The second kind of instability consists in the snap-back of the collector current Ic when the device is driven at constant emitter-base voltage VEB and can be explained by a simple model which takes into account the voltage drop induced by negative base current on the base spreading resistance.

1993 - Extension of impact-ionization multiplication coefficient measurements to high electric fields in advanced Si BJTs [Articolo su rivista]
E., Zanoni; Ef, Crabbe; Jmc, Stork; Pavan, Paolo; Verzellesi, Giovanni; L., Vendrame; Canali, Claudio
abstract

Measurements of the impact-ionization multiplication coefficient M - 1 in advanced Si BJT's up to values in excess of 10 (corresponding to a peak electric field at the base-collector junction of about 9 . 10(5) V/cm) are presented. The intrinsic limitations affecting M - 1 measurements at high electric fields are discussed. In particular, the fundamental role played by the negative base current and the parasitic base resistance in determining instabilities during M - 1 measurements is pointed out An accurate theoretical prediction of the M - 1 coefficient at collector-base voltages close to BV(CBO) requires that the contribution of holes to impact ionization be properly accounted for.

1993 - Extraction of DC base parasitic resistance of bipolar transistors based on impact-ionization-induced base current reversal [Articolo su rivista]
Verzellesi, Giovanni; R., Turetta; Pavan, Paolo; A., Collini; A., Chantre; A., Marty; Canali, Claudio; E., Zanoni
abstract

A new method for the evaluation of the dc base parasitic resistance of bipolar transistors is described. The method is based on impact-ionization-induced base current reversal and enables the base resistance to be evaluated independently from the emitter parasitic resistance in a wide range of emitter current and collector-base voltage, without requiring any special device structure. The method can also extract the base resistance in impact-ionization regime, where current crowding due to negative base current induces an increase in base resistance at increasing emitter current.

1993 - HOT-ELECTRON ELECTROLUMINESCENCE IN ALGAAS/GAAS HETEROJUNCTION BIPOLAR-TRANSISTOR [Articolo su rivista]
Zanoni, E; Vendrame, L; Pavan, Paolo; Manfredi, M; Bigliardi, S; Malik, R; Canali, Claudio
abstract

When biased in the active region at high collector voltages, AlGaAs/GaAs single heterojunction bipolar transistors have been observed to emit light in the 1. 1-2.5 eV energy range. The spectral distribution of the emitted radiation results from the superimposition of (i) two peaks at about 1.4 and 2.1 eV, due to band-to-band recombination of cold electrons and holes, and (ii) a nearly exponential tail due to hot-electron-induced electroluminescence, whose intensity depends on reverse collector-base voltage. Moreover, a linear correlation has been found between the intensity of the bot-electron-induced electroluminescence and the current generated by impact ionization.

1993 - Impact ionization phenomena in AlGaAs/GaAs HBTs [Relazione in Atti di Convegno]
Di Carlo, A.; Lugli, P.; Pavan, P.; Zanoni, E.; Malik, R.
abstract

Ionization phenomena in AlGaAs/GaAs HBTs are theoretically and experimentally investigated. The measured multiplication factor correlates well to the results of a Monte Carlo simulation of the device, which also provides general microscopic details of the pre-avalanche regime, and evidences the role of dead-space effects.

1993 - Impact-ionization effects in advanced Si bipolar transistors [Capitolo/Saggio]
Verzellesi, Giovanni; Pavan, Paolo; E., Zanoni; Canali, Claudio
abstract

Non disponibile

1993 - Improving reliability and safety of automotive electronics: research activities within the PROMETHEUS project [Articolo su rivista]
E., Zanoni; Pavan, Paolo
abstract

Microelectronics systems designed for automotive applications face an extremely hostile electrical and physical environment. Designers must produce increased component and system reliability while maintaining required compactness and cost effectiveness levels. Their designs become crucial to all as we devote more electronic systems to safety-critical applications. We summarizee the results of the European Prometheus PRO-CHIP research groups working on the reliability and fail-safe operation of microelectronic systems and devices.

1993 - Measurement of the electron impact-ionization coefficient in <100> GaAs at low electric fields by means of AlGaAs/GaAs Heterojunction Bipolar Transistors [Relazione in Atti di Convegno]
C., Canali; R. J., Malik; A., Neviani; Pavan, Paolo; C., Tedesco; E., Zanoni
abstract

In this work we discuss the factors limiting the M-1 measurements at low electric fields in lightly doped collector AlGaAs/GaAs HBT and extract the value of the electron ionization coefficient from the measured multiplication factor down to unity, extending previously available data.

1993 - Measurements of avalanche effects and light emission in advanced Si and SiGe bipolar transistors [Relazione in Atti di Convegno]
Zanoni, E.; Bigliardi, S.; Pavan, P.; Pisoni, P.; Canali, C.
abstract

In this paper we present the first measurements of the light emitted by advanced npn bipolar transistors in the 1.1 - 2.7 eV energy range. Light emitted by recombination in the forward biased BE junction dominates the spectra in the low-energy, 1.1 - 1.3 eV region, while hot-electron-induced light emission in the collector region dominates for photon energies above 1.5 eV and markedly depends on the applied VCB. The distribution of the high energy photons is nearly maxwellian with equivalent temperatures ranging from 1500 K at VCB= 1.45V to 2700 K at VCB = 3.75V, furthermore their intensity results in a linear relationship with both the collector current and the avalanche-induced current.

1993 - New method for extracting collector series resistance of bipolar transistors [Articolo su rivista]
Verzellesi, Giovanni; Turetta, R.; Cappellin, M.; Pavan, Paolo; Chantre, A.; Zanoni, E.
abstract

A new technique for extracting the collector series resistance of bipolar transistors is presented. The method is based on impact-ionisation-induced base current reversal and provides the value which the collector resistance assumes in the forward active region of operation.

1993 - Prediction of impact-ionization-induced snap-back in advanced Si n-p-n BJTs by means of a non-local analytical model for the avalanche multiplication factor [Articolo su rivista]
Verzellesi, Giovanni; Baccarani, G.; Canali, Claudio; Pavan, Paolo; Vendrame, L.; Zanoni, E.
abstract

When a triangular shape for the electric field in the base-collector space-charge region of an n-p-n Si BJT (bipolar junction transistor) is assumed, the electron mean energy can be calculated analytically from a simplified energy-balance equation. On this basis a nonlocal-impact-ionization model, suitable for computer-aided circuit simulation, has been obtained and used to calculate the output characteristics at constant emitter-base voltage (grounded base) of advanced devices. Provided the experimental bias-dependent value of the base parasitic resistance is accounted for in the device model, the base-collector voltage at which impact-ionization-induced snap-back occurs can be accurately predicted.

1992 - A new experimental technique for extracting base resistance and characterizing current crowding phenomena in bipolar transistors [Relazione in Atti di Convegno]
Verzellesi, Giovanni; L., Vendrame; R., Turetta; Pavan, Paolo; A., Chantre; A., Marty; M., Cavone; R., Rivoir; E., Zanoni
abstract

A new dc technique for extracting parasitic base resistance, RB, of advanced bipolar transistors is described. The technique is based on impact-ionization-induced base current reversal and enables RB to be measured as a function of collector-base voltage and of emitter current. To obtain accurate results, the influence of the Early effect on the emitter-base voltage at constant emitter current must be accounted for. Measured values of R, are correlated with current crowding phenomena, which can be directly observed by means of emission microscopy.

1992 - A study of ESD induced effects in high-voltage n-MOS and p-MOS transistors [Articolo su rivista]
Pavan, Paolo; E., Zanoni; B., Bonati; S., Martino; G., Dalla Libera
abstract

The optical beam induced current (OBIC) technique in a scanning laser microscope enables gate oxide shorts in MOS transistors to be detected and localized, and confirms results of electrical measurements performed on failed devices. The technique is completely non-destructive and can be applied to a large number of MOS gate oxide failures due to breakdown phenomena.

1992 - A study of ESD- induced defects in high-voltage nMOS and pMOS transistors [Articolo su rivista]
Pavan, P.; Zanoni, E.; Bonati, B.; Martion, S.; Libera, G. D.
abstract

The optical beam induced current (OBIC) technique in a scanning laser microscope enables gate oxide shorts in MOS transistors to be detected and localized, and confirms results of electrical measurements performed on failed devices. The technique is completely non-destructive and can be applied to a large number of MOS gate oxide failures due to breakdown phenomena. © 1992.

1992 - Explanation of current crowding phenomena induced by impact ionization in advanced Si bipolar transistors by means of electrical measurements and light emission microscopy [Articolo su rivista]
Pavan, Paolo; L., Vendrame; S., Bigliardi; A., Marty; A., Chantre; E., Zanoni
abstract

This paper analyzes impact ionization phenomena in advanced polysilicon emitter bipolar transistors. Two intrinsic limitations affecting multiplication coefficient at high electric fields are discussed. Emission microscopy is adopted to directly investigate and observe current crowding effects at the basis of the first kind of instability, which takes place when the device is driven at constant emitter current IE. The second kind of instability consists in the snap- back of the collector current Ic when the device is driven at constant emitter-base voltage VEB and can be explained by a simple model which takes into account the voltage drop induced by negative base current on the base spreading resistance.

1992 - Impact ionization and light emission phenomena in AlGaAs/GaAs HBT's [Relazione in Atti di Convegno]
Pavan, Paolo; E., Zanoni; L., Vendrame; R., Malik; S., Bigliardi; M., Manfredi; A., Di Carlo; P., Lugli; C., Canali
abstract

A combined experimental and theoretical evaluation of impact ionization effects in AlGaAs HBT's is presented. The measured multiplication factor correlates well to the results of a Monte Carlo simulation of the device, which evidences the role of secondary carriers in determining the breakdown voltage. The spectral distribution of the light emitted by the device is analyzed, and its intensity is correlated with base current changes due to impact ionization.

1992 - Impact-ionization phenomena in AlGaAs/GaAs HBT's [Articolo su rivista]
A., Di Carlo; P., Lugli; Pavan, Paolo; E., Zanoni; R., Malik
abstract

Ionization phenomena in A1GaAs/GaAs HBTs are theoretically and experimentally investigated. The measured multiplication factor correlates well to the results of a Monte Carlo simulation of the device, which also provides general microscopic details of the pre-avalanche regime, and evidences the role of dead-space effects.

1992 - Measurements and simulation of avalanche breakdown in advanced Si bipolar transistors [Relazione in Atti di Convegno]
E., Zanoni; E. F., Crabbe; J. M. C., Stork; Pavan, Paolo; Verzellesi, Giovanni; L., Vendrame; Canali, Claudio
abstract

A complete analytical model for impact ionization effects in bipolar transistors, which is able to predict the behaviour of advanced devices up to breakdown, is presented. A simple expression of the carrier mean energy suitable for circuit simulation is used to calculate the device multiplication coefficient and enables the influence of non-equilibrium transport on impact ionization to be accounted for. The role played by the reverse base current in determining the snapback of the common base output characteristics is investigated both experimentally and theoretically.

1992 - NEGATIVE BASE CURRENT AND IMPACT IONIZATION PHENOMENA IN ALGAAS/GAAS HBTS [Articolo su rivista]
Zanoni, E; Malik, R; Pavan, Paolo; Nagle, J; Paccagnella, A; Canali, Claudio
abstract

Impact ionization phenomena in the collector region of AlGaAs/GaAs heterojunction bipolar transistors give rise to base current reduction and reversal. These phenomena can be characterized by extracting the M - 1 coefficient, which can be evaluated by measuring base current changes. Measurements of M - 1 are affected at low current densities by the presence of the collector-base junction reverse current I(CBO). At high current densities, three effects contribute to lower the measured M - 1 value: voltage drops due to R(C) and R(B) parasitic resistances, device self-heating, and lowering of the base-collector junction electric field due to mobile carriers. By appropriately choosing the emitter current value, parasitic phenomena are avoided and the behavior of M - 1 as a function of the collector-base voltage V(CB) in AlGaAs/GaAs HBT's is accurately characterized.

1992 - Negative base current, impact-ionization and light emission phenomena in AlGaAs/GaAs HBT's [Relazione in Atti di Convegno]
E., Zanoni; R., Malik; J., Nagle; Pavan, Paolo; L., Vendrame; C., Canali
abstract

This paper characterizes avalanche phenomena in AlGaAs/GaAs heterojunction Bipolar Transistors by measuring the reduction and reversal of the base current induced by impact ionization. Light emitted by AlGaAs/GaAs HBTs has been measured in the 1.1 - 2.7 eV energy range.

1992 - Transiently triggered latch-up in CMOS twin-tub and epitaxial technologies [Articolo su rivista]
Pavan, Paolo; P., Caprara; M., Stucchi; E., Zanoni
abstract

We present in this work and analysis of transiently triggered latch-up in test-structures fabricated using a twin-tub process implemented on two different substrates: a p-type and a p/p+ epitaxial one. Steady-state electrical characterization confirmed the well-known increased latch-up resistance of epitaxial structures with respect to standard ones. In this paper it is shown that, depending on the chosen electrical configuration, when latch-up is transiently triggered, epitaxial structures may have dynamic triggering currents lower that twin-tub ones. The influence of some layout variables on turn on threshold voltage has been investigated for all samples.

1991 - Adjacent structure interactions in latch-up dc triggering of CMOS twin-tub and epitaxial technologies [Relazione in Atti di Convegno]
Pavan, Paolo; Zanoni, E.; Menozzi, R.; Selmi, L.
abstract

In this paper a bulk twin-tub and an epitaxial CMOS technology are studied from the viewpoint of latch-up hardness reduction due to interaction between adjacent structures, by means of static triggering measurements performed on "ad hoc" test patterns. The experimental results indicate that such interactions can seriously increase the latch-up susceptibility of the devices under test in the case of the bulk twin-tub process, while the epitaxial one shows in general better stability of the latch-up behavior.

1991 - Adjacent structure interactions in the Latch-up triggering of CMOS twin-tub and epitaxial technologies [Relazione in Atti di Convegno]
Pavan, P; Zanoni, E; Menozzi, R; Selmi, Luca
abstract

1991 - Analysis of dc and ac anomalous latch-up effects in commercial CMOS integrated circuits [Articolo su rivista]
E., Zanoni; Pavan, Paolo; G., Spiazzi; B., Bonati; C., Canali
abstract

Anomalous effects in electrical latch-up characteristics have been identified both in the d.c. (hysteresis effects) and a.c. (window effects) characteristics of a large sample of commercial CMOS ICs of different suppliers and technologies. Both d.c. and a.c. effects were always present in all tested devices which showed anomalies, Infra-red microscopy and scanning laser microscopy reveal that both effects are caused by current redistribution between different latch-up paths and are therefore correlated.

1991 - Latch-up dc triggering and holding characteristics of n-well, twin-tub and epitaxial CMOS technologies [Articolo su rivista]
Pavan, Paolo; G., Spiazzi; E., Zanoni; M., Muschitiello; M., Cecchetti
abstract

The dependence of the latch-up susceptibility on layout parameters is studied on four stripe structures made using different CMOS pro- cesses: a standard n-well, a twin-tub and twin-tub epitaxial technology. The correlation between triggering currents, well and substrate resistances and parasitic transistor gains is studied by means of emitter current triggering measurements and two- dimensional simulations using HFIELDS. Triggering currents higher than 250 mA are obtained on epitaxial structures with n+ guard-rings. Anomalies in triggering and holding electrical characteristics are caused by the three-dimensional distribution of the latch-up current, which is observed by IR microscopy. These anomalies can affect results of conventional latch-up testing methods.

1991 - Measurements of avalanche effects and light emission in advanced Si and SiGe bipolar transistors [Articolo su rivista]
E., Zanoni; S., Bigliardi; Pavan, Paolo; P., Pisoni; C., Canali
abstract

In this paper we present the first measurements of the light emitted by advanced npn bipolar transistors in the 1.1 - 2.7 eV energy range. Light emitted by recombination in the forward biased BE junction dominates the spectra in the low-energy, 1.1 - 1.3 eV region, while hot- electron-induced light emission in the collector region dominates for photon energies above 1.5 eV and markedly depends on the applied VCB.The distribution of the high energy photons is nearly maxwellian with equivalent temperatures ranging from 1500 K at VCB=1.45V to 2700 K at VCB = 3.75V, furthermore their intensity results in a linear relationship with both the collector current and the avalanche-induced current.

1991 - Transiently triggered latch-up in CMOS twin-tub and epitaxial technologies [Relazione in Atti di Convegno]
Pavan, Paolo; P., Caprara; B., Bonati; E., Zanoni
abstract

We present in this work an analysis of transiently triggered latch-up in test structures fabricate using a twin-tub process implemented on two different substrates: a p-type and a p/p+ epitaxial one. Steady-state electrical characterization confirmed the well-known increased latch-up resistance of epitaxial structures with respect to standard ones. In this paper it is shown that, depending on the chosen electrical configuration, when latch-up is transiently triggered, epitaxial structures may have dynamic triggering currents lower than twin-tub ones. The influence of some layout variables on turn-on threshold voltage has been investigated for all samples.

1990 - The dependence of latch-up sensitivity on layout and technology features, as analyzed by electrical measurements, HFIELDS and SPICE simulations, and infrared microscopy characterization [Relazione in Atti di Convegno]
E., Zanoni; G., Spiazzi; Pavan, Paolo; M., Cecchetti; M., Muschitiello
abstract

The influence of different layout parameters and of temperature on latch-up susceptibility has been studied on standard four-stripes test structures made using different processes: a standard n-well, a twin-tub and an epitaxial technology. Triggering characteristics of structures without guard rings can be fairly accurately predicted by two-dimensional simulations, performed by HFIELDS. Hysteresis effects in the holding characteristics are due to an uneven distribution of latch-up current within the structures, which has been detected by IR microscopy. Similar current redistribution effects can cause anomalies during pulsed measurements on CMOS integrated circuits. Three-diemsnional effects can be emulated by SPICE simulations.