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2023 - Negative Capacitors and Applications [Capitolo/Saggio]
Ashraful Alam, Muhammad; Zagni, Nicolo'; Kumar Saha, Atanu; Thakuria, Niharika; Thirumala, Sandeep; Kumar Gupta, Sumeet

The long-standing tug-of-war between off-state leakage power consumption and switching speed has posed severe challenges to the scaling of semiconductor devices. Deeply scaled short-channel transistors are faster but consume more off-state power. This power vs speed trade-off stems from the fundamental physical limit related to the thermionic emission that governs switching in field-effect transistors. There is a broad consensus in the semiconductor industry that future progress is impossible unless the next-generation transistors and circuits overcome the so-called Boltzmann limit associated with thermionic emission over a barrier and offer a steeper on-off switching to enable a more aggressive voltage scaling. In this chapter, we explain the need for and suggest an intuitive classification of the emerging transistor technologies. We use two illustrative examples of next-generation transistors (i.e., negative capacitance FET (NCFET) and phase FET (PhaseFET)) to explain the relative merits of gate-controlled vs channel-controlled steep-slope switching. We explain the basic principle of device operation, summarize the experimental results reported in the literature, and highlight the speed and reliability challenges to be resolved before the devices are integrated into practical systems. In addition, the chapter includes a careful analysis of circuits based on these emerging transistor technologies with applications toward Boolean logic, memories, and non-Boolean computing. The analysis suggests relative merits of various circuit designs and applications pecific opportunities for significant power-performance improvement.

2023 - Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges [Articolo su rivista]
Zagni, Nicolo'; Puglisi, Francesco Maria; Pavan, Paolo; Alam, Muhammad Ashraful

Ferroelectric transistors (FeFETs) based on doped hafnium oxide (HfO2) have received much attention due to their technological potential in terms of scalability, highspeed, and low-power operation. Unfortunately, however, HfO2-FeFETs also suffer from persistent reliability challenges, specifically affecting retention, endurance, and variability. A deep understanding of the reliability physics of HfO2-FeFETs is an essential prerequisite for the successful commercialization of this promising technology. In this article, we review the literature about the relevant reliability aspects of HfO2-FeFETs. We initially focus on the reliability physics of ferroelectric capacitors, as a prelude to a comprehensive analysis of FeFET reliability. Then, we interpret key reliability metrics of the FeFET at the device level (i.e., retention, endurance, and variability) based on the physical mechanisms previously identified. Finally, we discuss the implications of device-level reliability metrics at both the circuit and system levels. Our integrative approach connects apparently unrelated reliability issues and suggests mitigation strategies at the device, circuit, or system level. We conclude this article by proposing a set of research opportunities to guide future development in this field.

2022 - A Novel Temperature Estimation Technique Exploiting Carrier Emission from Buffer Traps [Relazione in Atti di Convegno]
Cioni, Marcello; Zagni, Nicolo; Chini, Alessandro

We propose a novel technique for temperature estimation in electron devices based on the mutual correlation between emission time constant from traps ( τ ) and temperature ( T ). Arrhenius equation is employed as the physical model relating τ and T The reference system used to present the technique is AlGaN/GaN high electron mobility transistors (HEMTs) with Fe-doping in the buffer. Drain Current Transients (DCTs) are used for extracting the emission time constant ( τ ) from Fe traps and non-linear regression through Trust Region Reflective (TRR) optimization algorithm is used to learn the model parameters from data and infer device temperature. Electro-thermal device simulations are employed for validating the proposed technique, showing that this method is able to provide an improved accuracy with respect to conventional electrical techniques (e.g., McAlister method) promoting it as a valid alternative to state of-the-art optical techniques in GaN HEMTs.

2022 - Experimental and numerical investigation of Poole-Frenkel effect on dynamic RON transients in C-doped p-GaN HEMTs [Articolo su rivista]
Zagni, Nicolò; Cioni, Marcello; Iucolano, Ferdinando; Moschetti, Maurizio; Verzellesi, Giovanni; Chini, Alessandro

In this paper, we investigate the influence of Poole-Frenkel Effect (PFE) on the dynamic RON transients in C-doped p-GaN HEMTs. To this aim, we perform a characterization of the dynamic RON transients acquired during OFF-state stress (i.e., VGS,STR = 0 V < VT, VDS,STR = 25–125 V) and we interpret the results with the aid of numerical simulations. We find that dynamic RON transients at room temperature accelerate with VDS,STR1/2, which is signature of PFE, as further confirmed by the simultaneous decrease of the activation energy (EA) extracted from the Arrhenius plot of the dynamic RON transients at VDS,STR = 50 V and T = 30–110 °C. Results obtained by means of calibrated numerical simulations reproduce the exponential dependence of transients time constants (τ) on VDS,STR1/2 and consequent EA reduction only when including PFE enhancement of hole emission from dominant acceptor traps in the buffer related to C doping. This result is consistent with the model that considers hole emission from acceptor traps (rather than electron capture) as the mechanism underlying dynamic RON increase during OFF-state stress.

2022 - Fe-Traps Influence on Time-dependent Breakdown Voltage in 0.1-μm GaN HEMTs for 5G Applications [Relazione in Atti di Convegno]
Cioni, M.; Zagni, N.; Chini, A.

Scaled (LG = 0.1 μm) GaN HEMT technology is currently pursued for high-frequency applications (such as 5G), requiring high current/speed and blocking capability. However, traps introduced with intentional Fe doping yield time-dependent breakdown voltage (VBR), seriously affecting reliability. Here, we investigate the role of Fe traps by pulsed I-V characterization performed at different pulse durations (TOFF). A TOFF-dependent VBR is observed on tested devices and is ascribed to the time-dependent occupancy of deep acceptors in the buffer layer. More specifically, the decrease in VBR for short pulses is attributed to the increased leakage due to the reduced ionization of Fe-traps. This interpretation is supported by 2D numerical simulations.

2022 - Role of carbon in dynamic effects and reliability of 0.15-um AlGaN/GaN HEMTs for RF power amplifiers [Relazione in Atti di Convegno]
De Santi, Carlo; Zanoni, Enrico; Meneghini, Matteo; Meneghesso, Gaudenzio; Rampazzo, Fabiana; Gao, Veronica Zhan; Sharma, Chandan; Chiocchetta, Francesca; Verzellesi, Giovanni; Chini, Alessandro; Cioni, Marcello; Zagni, Nicolò; Lanzieri, Claudio; Pantellini, Alessio; Peroni, Marco; Latessa, Luca

This paper presents results concerning the dynamic performance and reliability of Fe-doped and C-doped 0.15-m gate AlGaN/GaN HEMTs. Step-stress tests at increasing drain-source voltage and different gate-source voltages are specifically reported. Fe-doped HEMTs exhibit, under both off- and on-state conditions, excellent parametric stability up to breakdown. C-doped devices are instead affected by enhanced degradation effects during the step stress experiments compared to Fe-doped ones, consisting of RON increase during off-state stress and both threshold-voltage and RON increase under on-state conditions. 2D hydrodynamic device simulations are used to validate hypotheses on the physical mechanisms underlying the observed, distinctive degradation effects. The role of C doping in causing additional degradation compared to Fe-doped device is explained with the aid of device simulations as follows: 1) under off-state conditions, hole emission from the CN acceptor traps in the gate-drain region of the buffer leads to an RON increase which is not completely recovered during the typical recovery time interval following each stress phase and therefore accumulates during the step stress experiment; 2) under on-state conditions, channel hot electrons are injected (besides towards the surface) into the buffer where they can be captured by CN traps under the gate and in the gate-drain region, inducing semi-permanent threshold-voltage and RON increases.

2022 - Symmetrical VTH/RONDrifts Due to Negative/Positive Gate Stress in p-GaN Power HEMTs [Relazione in Atti di Convegno]
Zagni, N.; Cioni, M.; Castagna, M. E.; Moschetti, M.; Iucolano, F.; Verzellesi, G.; Chini, A.

2022 - Temperature-Independent Current Dispersion in 0.15 μm AlGaN/GaN HEMTs for 5G Applications [Articolo su rivista]
Zagni, Nicolo'; Verzellesi, Giovanni; Chini, Alessandro

Thanks to high-current densities and cutoff frequencies, short-channel length AlGaN/GaN HEMTs are a promising technology solution for implementing RF power amplifiers in 5G front-end modules. These devices, however, might suffer from current collapse due to trapping effects, leading to compressed output power. Here, we investigate the trap dynamic response in 0.15 μm GaN HEMTs by means of pulsed I-V characterization and drain current transients (DCTs). Pulsed I-V curves reveal an almost absent gate-lag but significant current collapse when pulsing both gate and drain voltages. The thermally activated Arrhenius process (with EA ≈ 0.55 eV) observed during DCT measurements after a short trap-filling pulse (i.e., 1 μs) indicates that current collapse is induced by deep trap states associated with iron (Fe) doping present in the buffer. Interestingly, analogous DCT characterization carried out after a long trap-filling pulse (i.e., 100 s) revealed yet another process with time constants of about 1–2 s and which was approximately independent of temperature. We reproduced the experimentally observed results with two-dimensional device simulations by modeling the T-independent process as the charging of the interface between the passivation and the AlGaN barrier following electron injection from the gate.

2021 - Effect of Trap-Filling Bias on the Extraction of the Time Constant of Drain Current Transients in AlGaN/GaN HEMTs [Relazione in Atti di Convegno]
Zagni, Nicolo; Cioni, Marcello; Chini, Alessandro

2021 - Electric Field and Self-Heating Effects on the Emission Time of Iron Traps in GaN HEMTs [Articolo su rivista]
Cioni, Marcello; Zagni, Nicolo; Selmi, Luca; Meneghesso, Gaudenzio; Meneghini, Matteo; Zanoni, Enrico; Chini, Alessandro

In this paper we separately investigate the role of electric field and device self-heating (SHE) in enhancing the charge emission process from Fe-related buffer traps (0.52 eV from Ec) in AlGaN/GaN High Electron Mobility Transistors (HEMTs). The experimental analysis was performed by means of Drain Current Transient (DCT) measurements for either i) different dissipated power (PD,steady) at constant drain-to-source bias (VDS,steady) or ii) constant PD,steady at different VDS,steady. We found that i) an increase in PD,steady yields an acceleration in the thermally activated emission process, consistently with the temperature rise induced by SHE. On the other hand, ii) the field effect turned out to be negligible within the investigated voltage range, indicating the absence of Poole-Frenkel effect (PFE). A qualitative analysis based on the electric field values obtained by numerical simulations is then presented to support the interpretation and conclusions.

2021 - Evaluation of VTH and RON Drifts during Switch-Mode Operation in Packaged SiC MOSFETs [Articolo su rivista]
Cioni, Marcello; Bertacchini, Alessandro; Mucci, Alessandro; Zagni, Nicolò; Verzellesi, Giovanni; Pavan, Paolo; Chini, Alessandro

In this paper, we investigate the evolution of threshold voltage (VTH) and on-resistance (RON) drifts in the silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) during the switch-mode operation. A novel measurement setup for performing the required on-the-fly characterization is presented and the experimental results, obtained on commercially available TO-247 packaged SiC devices, are reported. Measurements were performed for 1000 s, during which negative VTH shifts (i.e., VTH decrease) and negative RON drifts (i.e., RON decrease) were observed. To better understand the origin of these parameter drifts and their possible correlation, measurements were performed for different (i) gate-driving voltage (VGH) and (ii) off-state drain voltage (VPH). We found that VTH reduction leads to a current increase, thus yielding RON to decrease. This correlation was explained by the RON dependence on the overdrive voltage (VGS–VTH). We also found that gate-related effects dominate the parameter drifts at low VPH with no observable recovery, due to the repeated switching of the gate signal required for the parameter monitoring. Conversely, the drain-induced instabilities caused by high VPH are completely recoverable within 1000 s from the VPH removal. These results show that the measurement setup is able to discern the gate/drain contributions, clarifying the origin of the observed VTH and RON drifts.

2021 - GaN-based power devices: Physics, reliability, and perspectives [Articolo su rivista]
Meneghini, Matteo; De Santi, Carlo; Abid, Idriss; Buffolo, Matteo; Cioni, Marcello; Khadar, Riyaz Abdul; Nela, Luca; Zagni, Nicolò; Chini, Alessandro; Medjdoub, Farid; Meneghesso, Gaudenzio; Verzellesi, Giovanni; Zanoni, Enrico; Matioli, Elison

Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semicon- ductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spon- taneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high- voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench- structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main proper- ties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.

2021 - Highly sensitive active pixel image sensor array driven by large-area bilayer MoS2 transistor circuitry [Articolo su rivista]
Hong, Seongin; Zagni, Nicolo'; Choo, Sooho; Liu, Na; Baek, Seungho; Bala, Arindam; Yoo, Hocheon; Ha Kang, Byung; Jae Kim, Hyun; Joong Yun, Hyung; Ashraful Alam, Muhammad; Kim, Sunkook

Various large-area growth methods for two-dimensional transition metal dichalcogenides have been developed recently for future electronic and photonic applications. However, they have not yet been employed for synthesizing active pixel image sensors. Here, we report on an active pixel image sensor array with a bilayer MoS2 film prepared via a two-step large-area growth method. The active pixel of image sensor is composed of 2D MoS2 switching transistors and 2D MoS2 phototransistors. The maximum photoresponsivity (Rph) of the bilayer MoS2 phototransistors in an 8 × 8 active pixel image sensor array is statistically measured as high as 119.16 AW−1. With the aid of computational modeling, we find that the main mechanism for the high Rph of the bilayer MoS2 phototransistor is a photo-gating effect by the holes trapped at subgap states. The image-sensing characteristics of the bilayer MoS2 active pixel image sensor array are successfully investigated using light stencil projection.

2021 - Mechanisms Underlying the Bidirectional VT Shift After Negative-Bias Temperature Instability Stress in Carbon-Doped Fully Recessed AlGaN/GaN MIS-HEMTs [Articolo su rivista]
Zagni, Nicolo; Cioni, Marcello; Chini, Alessandro; Iucolano, Ferdinando; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni

In this brief, we investigate the bidirectional threshold voltage drift (VT) following negative-bias temperature instability (NBTI) stress in carbon-doped fully recessed AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Several stress conditions were applied at different: 1) gate biases (VGS,STR); 2) stress times (tSTR); and 3) temperatures (T). Both negative and positive VT (thermally activated with different activation energies, EA) were observed depending on the magnitude of VGS,STR. In accordance with the literature, observed VT < 0 V (EA ≈ 0.5 eV) under moderate stress is attributed to the emission of electrons from oxide and interface traps. Instead, VT > 0 V (EA ≈ 0.9 eV) under high stress is attributed to the increased negatively ionized acceptor trap density in the buffer associated with carbon doping.

2021 - Modeling Nanoscale III–V Channel MOSFETs with the Self-Consistent Multi-Valley/Multi-Subband Monte Carlo Approach [Articolo su rivista]
Caruso, Enrico; Esseni, David; Gnani, Elena; Lizzit, Daniel; Palestri, Pierpaolo; Pin, Alessandro; Puglisi, Francesco Maria; Selmi, Luca; Zagni, Nicolò

We describe the multi-valley/multi-subband Monte Carlo (MV–MSMC) approach to model nanoscale MOSFETs featuring III–V semiconductors as channel material. This approach describes carrier quantization normal to the channel direction, solving the Schrödinger equation while off-equilibrium transport is captured by the multi-valley/multi-subband Boltzmann transport equation. In this paper, we outline a methodology to include quantum effects along the transport direction (namely, source-to-drain tunneling) and provide model verification by comparison with Non-Equilibrium Green’s Function results for nanoscale MOSFETs with InAs and InGaAs channels. It is then shown how to use the MV–MSMC to calibrate a Technology Computer Aided Design (TCAD) simulation deck based on the drift–diffusion model that allows much faster simulations and opens the doors to variability studies in III–V channel MOSFETs.

2021 - On the Modeling of the Donor/Acceptor Compensation Ratio in Carbon‐Doped GaN to Univocally Reproduce Breakdown Voltage and Current Collapse in Lateral GaN Power HEMTs [Articolo su rivista]
Zagni, Nicolo'; Chini, Alessandro; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni

The intentional doping of lateral GaN power high electron mobility transistors (HEMTs) with carbon (C) impurities is a common technique to reduce buffer conductivity and increase breakdown voltage. Due to the introduction of trap levels in the GaN bandgap, it is well known that these impurities give rise to dispersion, leading to the so‐called “current collapse” as a collateral effect. Moreover, first‐principles calculations and experimental evidence point out that C introduces trap levels of both acceptor and donor types. Here, we report on the modeling of the donor/acceptor compensation ratio (CR), that is, the ratio between the density of donors and acceptors associated with C doping, to consistently and univocally reproduce experimental breakdown voltage (VBD) and current‐collapse magnitude (ΔICC). By means of calibrated numerical device simulations, we confirm that ΔICC is controlled by the effective trap concentration (i.e., the difference between the acceptor and donor densities), but we show that it is the total trap concentration (i.e., the sum of acceptor and donor densities) that determines VBD, such that a significant CR of at least 50% (depending on the technology) must be assumed to explain both phenomena quantitatively. The results presented in this work contribute to clarifying several previous reports, and are helpful to device engineers interested in modeling C‐doped lateral GaN power HEMTs.

2021 - Partial Recovery of Dynamic RON Versus OFF-State Stress Voltage in p-GaN Gate AlGaN/GaN Power HEMTs [Articolo su rivista]
Cioni, Marcello; Zagni, Nicolo; Iucolano, Ferdinando; Moschetti, Maurizio; Verzellesi, Giovanni; Chini, Alessandro

Dynamic Ron dispersion due to buffer traps is a well-known issue of GaN power high electron mobility transistors (HEMTs), critically impacting their performance and stability. Several works show that the dynamic Ron reaches a maximum for some off-state drain-source voltage ( VDS,off ) value typically in the range of several hundred volts and then partially recovers to smaller values. In this work, we propose a quantitative explanation for this behavior, attributing it to the charging/discharging dynamics of carbon (C)-related buffer traps. We characterize the dynamic Ron in packaged p-GaN gate AlGaN/GaN HEMTs with a custom measurement setup. We find that in these devices, the relative Ron increase reaches a maximum of 60% for VDS,off≈100 -200 V, partially recovering to about 30% as VDS,off is raised to 500 V. We ascribe this behavior to the partial neutralization of C-related acceptor traps in the buffer due to trapping of holes produced by a high-field generation mechanism. This explanation is supported by calibrated 2-D numerical simulations, that successfully reproduce the experimentally observed Ron reduction only when including a hole generation mechanism.

2021 - Reliability physics of ferroelectric/negative capacitance transistors for memory/logic applications: An integrative perspective [Articolo su rivista]
Zagni, Nicolo'; Ashraful Alam, Muhammad

Despite the remarkable development in ferroelectric HfO2-based FETs, key reliability challenges (e.g., retention, endurance, etc.) may still limit their widespread adoption in memory and logic applications. In this paper, we present a simple theoretical framework—based on the Landau theory of phase transition—to design both ferroelectric FETs (FeFETs) and negative capacitance transistors (NCFETs) and investigate their reliability issues. For FeFETs, we analyze the role of interface and bulk traps on memory window closure to quantify endurance under different operating conditions. For NCFETs, we discuss the beneficial role of NC effect in reducing (or even eliminating) the persistent reliability issue of negative bias temperature instability that has plagued MOSFETs for decades. FE/NCFETs can also be affected by the Hot Atom Damage involving switching-induced bond dissociation during transient overshoot. We conclude by discussing how other FET reliability issues (e.g., TDDB, HCD, etc.) may also have to be reinterpreted for FE/NCFETs.

2021 - Self-Heating and Reliability-Aware “Intrinsic” Safe Operating Area of Wide Bandgap Semiconductors – An Analytical Approach [Articolo su rivista]
Mahajan, Bikram Kishore; Chen, Yen-Pu; Zagni, Nicolò; Alam, Muhammad Ashraful

The emergence of several technology options and the ever-broadening range of applications (e.g., automotive, smart grids, solar/wind farms) for power electronic devices suggest both a need and an opportunity to develop unifying principles to guide the development of wide bandgap (WBG) semiconductors. Unfortunately, power electronic devices are typically evaluated with a variety of elementary figure of merits (FOMs), which offer inconsistent/contradictory projections regarding the relative merits of emerging technologies. Indeed, one relies on the empirical (extrinsic) safe-operating area (SOA) of a packaged device to ultimately assess the performance potential of a technology option. Unfortunately, extrinsic SOA can only be calculated a posteriori, i.e., after precise measurement of the fabricated device parameters, making it suitable only for relatively mature technologies. Based on the insights of material-device-circuit-system performance analysis of a variety of idealized WBG power electronic devices (e.g., GaN HEMT, β-Ga2O3 MOSFET), in this paper, we analytically derive a comprehensive, substrate-, self-heating-, and reliability-aware “intrinsic/limiting” safe operating area (SOA) that establishes a priori, i.e., before device fabrication, the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability. We establish the relevance of the intrinsic-SOA by comparing its prediction with a broad range of experimental data available in the literature. In between the traditional FOMs and extrinsic SOA, the intrinsic SOA allows fundamental/intuitive re-evaluation of intrinsic technology potential for power electronic devices and identifies specific performance bottlenecks and how to circumvent them.

2021 - “Hole Redistribution” Model Explaining the Thermally Activated RON Stress/Recovery Transients in Carbon-Doped AlGaN/GaN Power MIS-HEMTs [Articolo su rivista]
Zagni, Nicolò; Chini, Alessandro; Puglisi, Francesco Maria; Meneghini, Matteo; Meneghesso, Gaudenzio; Zanoni, Enrico; Pavan, Paolo; Verzellesi, Giovanni

RON degradation due to stress in GaN-based power devices is a critical issue that limits, among other effects, long-term stable operation. Here, by means of 2-D device simulations, we show that the RON increase and decrease during stress and recovery experiments in carbon-doped AlGaN/GaN power metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) can be explained with a model based on the emission, redistribution, and retrapping of holes within the carbon-doped buffer (“hole redistribution” in short). By comparing simulation results with front- and back-gating OFF-state stress experiments, we provide an explanation for the puzzling observation of both stress and recovery transients being thermally activated with the same activation energy of about 0.9 eV. This finds a straightforward justification in a model in which both RON degradation and recovery processes are limited by hole emission by dominant carbon-related acceptors that are energetically located at about 0.9 eV from the GaN valence band.

2020 - A memory window expression to evaluate the endurance of ferroelectric FETs [Articolo su rivista]
Zagni, Nicolo'; Pavan, Paolo; Ashraful Alam, Muhammad

The recent discovery of ferroelectricity in HfO2 has revived the interest into non-volatile memories based on ferroelectric transistors (FeFETs). The key advantages of these FeFETs include the low power consumption and the compatibility with the existing CMOS process. On the other hand, issues related mainly to endurance still represent a challenge to the development of the technology. In this Letter, we propose to exploit an analytical expression for the Memory Window (MW) as a simple yet effective characterization tool to evaluate the endurance of FeFETs. The MW is defined as the difference between threshold voltages occurring due to polarization switching. The analytical formulation of the MW allows one to quickly estimate the generated trap concentration as a function of number of writing cycles (or time) without recurring to numerical simulations. With the aid of the analytical model, we find that for typical program/erase pulse amplitudes and duration, endurance has a weak dependence on writing conditions. The characterization technique based on the MW would allow the systematic comparison of the performance and endurance of next-generation FeFETs.

2020 - Characterization and TCAD Modeling of Mixed-Mode Stress Induced by Impact Ionization in Scaled SiGe HBTs [Articolo su rivista]
Zagni, Nicolo; Puglisi, Francesco Maria; Verzellesi, Giovanni; Pavan, Paolo

We investigate the reliability of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) in 55-nm technology under mixed-mode stress. We perform electrical characterization and implement a TCAD model calibrated on the measurement data to describe the increased base current degradation at different collector-base voltages. We introduce a simple and self-consistent simulation methodology that links the observed degradation trend to interface traps generation at the emitter/base spacer oxide ascribed to hot holes generated by impact ionization (II) in the collector/base depletion region. This effectively circumvents the limitations of commercial TCAD tools that do not allow II to be the driving force of the degradation. The approach accounts for self-heating and electric fields distribution allowing to reproduce measurement data including the deviation from the power-law behavior.

2020 - Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-Of-The-Roadmap III-V MOSFETs [Articolo su rivista]
Zagni, Nicolo'; Caruso, Enrico; Puglisi, Francesco Maria; Pavan, Paolo; Palestri, Pierpaolo; Verzellesi, Giovanni

Thanks to their superior transport properties, Indium Gallium Arsenide (InGaAs) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) constitute an alternative to conventional Silicon MOSFETs for digital applications at ultra-scaled nodes. The successful integration of this technology is challenged mainly by the high defect density in the gate oxide and at the interface with the semiconductor channel, which degrades the electrostatics and could limit the potential benefits over Si. In this work, we i) establish a systematic modeling approach to evaluate the performance degradation due to interface traps in terms of electrostatics and transport of InGaAs Dual-Gate Ultra-Thin Body (DG-UTB) FETs, and ii) investigate the effects of random interface-trap concentration as another roadblock to the scaling of the technology, due to statistical variability of the threshold voltage. Variability is assessed with a Technology CAD (TCAD) simulator calibrated against Multi-Subband Monte Carlo (MSMC) simulations. The modeling approach overcomes the TCAD limitations when dealing with ultra-thin channels (i.e., below 5 nm) without altering crucial geometrical parameters that would compromise the dependability of the variability analysis. Our results indicate that interface-trap fluctuation becomes comparable with the other variability sources dominating the total variability when shrinking the device dimensions, thus contrasting the trend of reduced variability with scaling. This in turn implies that interface and border traps may strongly limit the benefits of InGaAs over Silicon if not effectively reduced by gate process optimization.

2020 - The Role of Carbon Doping on Breakdown, Current Collapse and Dynamic On-Resistance Recovery in AlGaN/GaN High Electron Mobility Transistors on Semi‐Insulating SiC Substrates [Articolo su rivista]
Zagni, Nicolò; Chini, Alessandro; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni

In this work, the critical role of carbon doping in the electrical behavior of AlGaN/GaN High Electron Mobility Transistors (HEMTs) on semi-insulating SiC substrates is assessed by investigating the off-state three terminal breakdown, current collapse and dynamic on-resistance recovery at high drain-source voltages. Extensive device simulations of typical GaN HEMT structures are carried out and compared to experimental data from published, state-of-the-art technologies to: i) explain the slope of the breakdown voltage as a function of the gate-to-drain spacing lower than GaN critical electric field as a result of the non-uniform electrical field distribution in the gate-drain access region; ii) attribute the drain current collapse to trapping in deep acceptor states in the buffer associated with carbon doping; iii) interpret the partial dynamic on-resistance recovery after off-state stress at high drain-source voltages as a consequence of hole generation and trapping.

2020 - The effects of carbon on the bidirectional threshold voltage instabilities induced by negative gate bias stress in GaN MIS-HEMTs [Articolo su rivista]
Zagni, Nicolò; Chini, Alessandro; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni

In this paper, numerical device simulations are used to point out the possible contributions of carbon doping to the threshold voltage instabilities induced by negative gate bias stress in AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistors. It is suggested that carbon can have a role in both negative and positive threshold voltage shifts, as a result of (1) the changes in the total negative charge stored in the carbon-related acceptor traps in the GaN buffer, and (2) the attraction of carbon-related free holes to the device surface and their capture into interface traps or recombination with gate-injected electrons. For a proper device optimization of carbon-doped MIS-HEMTs, it is therefore important to take these mechanisms into account, in addition to those related to defects in the gate dielectric volume and interface which are conventionally held responsible for threshold voltage instabilities.

2020 - Trap Dynamics Model Explaining the RON Stress/Recovery Behavior in Carbon-Doped Power AlGaN/GaN MOS-HEMTs [Relazione in Atti di Convegno]
Zagni, Nicolo; Chini, Alessandro; Puglisi, Francesco Maria; Pavan, Paolo; Meneghini, Matteo; Meneghesso, Gaudenzio; Zanoni, Enrico; Verzellesi, Giovanni

In this paper, we present simulation results that reproduce stress and recovery experiments in Carbon-doped power GaN MOS-HEMTs and explain the associated R ON increase and decrease as the result of the emission, redistribution and re-trapping of holes within the Carbon-doped buffer. The proposed model can straightforwardly clarify the beneficial impact of the recently proposed p-type drain contact on R ON degradation as being a consequence of enhanced hole trapping and reduced negative trapped charge within the buffer during stress.

2019 - Effects of mole fraction variations and scaling on total variability in InGaAs MOSFETs [Articolo su rivista]
Zagni, N.; Puglisi, F. M.; Pavan, P.; Verzellesi, G.

Variability is one of the major roadblocks for III-V semiconductors in nanoscale devices, according to the recent International Roadmap for Devices and Systems (IRDS). A particular concern is the detrimental effect of variability of threshold voltage due to channel compositional variations. In this paper, we investigate the impact of this variability source and the effects of scaling on the performance of Dual-Gate-Ultra-Thin-Body (DG-UTB) In0.53Ga0.47As MOSFETs. We model mole fraction variations in terms of the Indium content by taking into account the spatial inhomogeneity of the channel and the corresponding bandgap variations, analyzing the effects on threshold voltage variability. We thus define a variability source, i.e., Band Gap Fluctuation (BGF), and we compare the associated variability with the ones from other important sources, namely, Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate-Line Edge Roughness (B-LER and G-LER). We then define three corner cases for mole fraction variations to determine worst-case variability. Finally, the impact of scaling on variability is assessed by comparing results for two technology nodes on the linear and saturation threshold voltage, V-T,V-lin,V- V-T,V-sat, on-current, I-ON, leakage current, I-OFF, and linear and saturation sub-threshold slope, SS. We find that although scaling has no impact on BGF-induced V-T variability, it increases the total V-T, lin variability as well as that for I-ON and I-OFF.

2019 - Halide Perovskite High-k Field Effect Transistors with Dynamically Reconfigurable Ambipolarity [Articolo su rivista]
Canicoba, Noelia Devesa; Zagni, Nicolò; Liu, Fangze; McCuistian, Gary; Fernando, Kasun; Bellezza, Hugo; Traoré, Boubacar; Rogel, Regis; Tsai, Hsinhan; Le Brizoual, Laurent; Nie, Wanyi; Crochet, Jared J.; Tretiak, Sergei; Katan, Claudine; Even, Jacky; Kanatzidis, Mercouri G.; Alphenaar, Bruce W.; Blancon, Jean-Christophe; Alam, Muhammad Ashraf; Mohite, Aditya D.

Despite the remarkable optoelectronic properties of halide perovskites, achieving reproducible field effect transistor (FET) action in polycrystalline films at room temperature has been challenging and represents a fundamental bottleneck for understanding electronic charge transport in these materials. In this work, we report halide perovskite-based FET operation at room temperature with negligible hysteresis. Extensive measurements and device modeling reveal that incorporating high-k dielectrics enables modulation of the channel conductance. Furthermore, continuous bias cycling or resting allows dynamical reconfiguration of the FETs between p-type behavior and ambipolar FET with balanced electron and hole transport and an ON/OFF ratio up to 104 and negligible degradation in transport characteristics over 100 cycles. These results elucidate the path for achieving gate modulation in perovskite thin films and provide a platform to understand the interplay between the perovskite structure and external stimuli such as photons, fields, and functional substrates, which will lead to novel and emergent properties.

2019 - Insights into the off-state breakdown mechanisms in power GaN HEMTs [Articolo su rivista]
Zagni, Nicolo'; Puglisi, F. M.; Pavan, P.; Chini, A.; Verzellesi, G.

We analyze the off-state, three-terminal, lateral breakdown in AlGaN/GaN HEMTs for power switching applications by comparing two-dimensional numerical device simulations with experimental data from device structures with different gate-to-drain spacing and with either undoped or Carbon-doped GaN buffer layer. Our simulations reproduce the different breakdown-voltage dependence on the gate-drain-spacing exhibited by the two types of device and attribute the breakdown to: i) a combination of gate electron injection and source-drain punch-through in the undoped HEMTs; and ii) avalanche generation triggered by gate electron injection in the C-doped HEMTs.

2019 - Two-dimensional MoS2 negative capacitor transistors for enhanced (super-Nernstian) signal-to-noise performance of next-generation nano biosensors [Articolo su rivista]
Zagni, N.; Pavan, P.; Alam, M. A.

The detection of biomolecules by a Field Effect Transistor-based biosensor (BioFET) is dictated by the sensor's intrinsic Signal-to-Noise Ratio (SNR). The detection limit of a traditional BioFET is fundamentally limited by biomolecule diffusion, charge screening, linear charge to surface-potential transduction, and Flicker noise. In this letter, we show that the recently introduced class of transistors called negative capacitor field effect transistors offers nonlinear charge transduction and suppression of Flicker noise to dramatically improve the SNR over classical Boltzmann sensors. We quantify the SNR improvement (approximately two orders of magnitude higher than a classical Si-nanowire biosensor) by interpreting the experimental results associated with the signal and noise characteristics of 2D MoS2-based transistors. The proposed Negative Capacitor BioFET (NC-BioFET) will motivate experimentalists to combine two well-established technologies to achieve high SNR (and to improve the detection limit), fundamentally unachievable by any other sensor technology.

2018 - Design and Optimization of β-Ga 2 O 3 on (h-BN layered) Sapphire for High Efficiency Power Transistors: A Device-Circuit-Package Perspective [Relazione in Atti di Convegno]
Mahajan, B. K.; Chen, Y. -P.; Ahn, W.; Zagni, N.; Alam, M. A.

Despite exceeding the Baliga's Figure of Merit (BFOM) by 400% and Huang's Chip Area Manufacturing FOM (HCAFOM) by 330% [1], the performance of existing β-Ga 2 O 3 FETs is inferior to that of GaN, primarily due to extreme self-heating. Self-heating effect (SHE) has emerged as an important concern for device performance, output power density, run-time variability and reliability for modern logic transistors. The effects are even more severe for high-power transistor where the channel material may be a poor thermal conductor, e.g. β-Ga 2 O 3 . Very high internal electric fields, extreme temperature and mechanical stresses associated with these transistors drive electrochemical reactions [2], influence atomic processes [3], and accelerate multiple non-equilibrium effects [4]. A device-circuit-package, multi-physics, multi-scale simulation is needed to capture these effects self-consistently, but such a model has not yet been developed. In this paper, we (i) develop the first self-consistent device (TCAD), circuit (HSPICE), and package (COMSOL) model considering SHE which predicts FET performance on variety of substrates accurately; (ii) use the model to propose a novel hexagonal-Boron Nitride (h-BN) based β-Ga 2 O 3 FET with 30% (cf. Sapphire substrate) and 80% (cf. SiO 2 substrate) reduction in thermal resistance (R th ); (iii) demonstrate the performance of boost converter (with parameters extracted from our TCAD model) with h-BN based β-Ga 2 O 3 FET, which outperforms the existing β-Ga 2 O 3 FETs, achieving an efficiency within 10-15% of highest performing enhancement mode (E-mode) GaN FET; (iv) propose h-BN based FinFET which exceeds the I ON of the existing β-Ga 2 O 3 FET by more than 500%; and (v) develop a Faraday-cage type novel packaging strategy for effective heat dissipation and efficient system performance in β-Ga 2 O 3 FETs.

2018 - Energy-efficient logic-in-memory I-bit full adder enabled by a physics-based RRAM compact model [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pacchioni, Lorenzo; Zagni, Nicolo; Pavan, Paolo

In this work, we explore the RRAM-based IMPLY logic by means of circuit simulations. Differently from previous works, we use a physics-based compact model of RRAM devices able to reproduce both the AC and the DC behavior, accounting for the intrinsic variability of the resistive states and the logic state degradation. A new implementation of a 1-bit full adder with unique properties for low-power circuits is proposed, and its performance in terms of energy consumption and execution time is evaluated by simulations. Results are compared against recent experiments, demonstrating a good agreement and indicating the direction for further improvement.

2018 - On the impact of channel compositional variations on total threshold voltage variability in nanoscale InGaAs MOSFETs [Relazione in Atti di Convegno]
Zagni, Nicolo; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni

In this paper we present an analysis of the impact of channel compositional variations on the total threshold voltage variability in nanoscale III-V MOSFETs. The analysis is carried out on a template Dual-Gate Ultra-Thin Body (DG-UTB) MOSFET through TCAD simulations in Sentaurus by Synopsys. The Impedance Field Method (IFM) is employed to evaluate statistical variability for five different sources: Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate-Line Edge Roughness (B-LER and G-LER) and Band Gap Fluctuation (BGF). BGF arises due to the compositional variations of Indium in the compound semiconductor composing the channel, namely InGaAs. Our analysis shows that, by appropriately modeling band gap fluctuations, it is possible to identify a worst-case total relative Vt variability for different amounts of Indium mole fraction variations, providing technologists with an important reference. Side-effects of channel compositional variations on other variability sources are evaluated as well, and are found to have a non-negligible impact on B-LER only.

2018 - Random Telegraph Noise in Resistive Random Access Memories: Compact Modeling and Advanced Circuit Design [Articolo su rivista]
Puglisi, Francesco Maria; Zagni, Nicolo; Larcher, Luca; Pavan, Paolo

In this paper, we report about the derivation of a physics-based compact model of random telegraph noise (RTN) in HfO2-based resistive random access memory (RRAM) devices. Starting from the physics of charge transport, which is different in the high resistive states and low resistive states, we explore the mechanisms responsible for RTN exploiting a hybrid approach, based on self-consistent physics simulations and geometrical simplifications. Then, we develop a simple yet effective physics-based compact model of RTN valid in both states, which can be steadily integrated in state-of-the-art RRAM compact models. The RTN compact model predictions are validated by comparison with both a large experimental data set obtained by measuring RRAM devices in different conditions, and data reported in the literature. In addition, we show how the model enables advanced circuit simulations by exploring three different circuits for memory, security, and logic applications.

2017 - A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Zagni, Nicolo'; Larcher, Luca; Pavan, Paolo

In this work, we propose for the first time a Verilog-A physics-based compact model of Random Telegraph Noise (RTN) in Resistive Random Access Memory (RRAM) devices. Starting from the physics of the RTN mechanism in both high (HRS) and low (LRS) resistive states, and combining experimental data with physics-based simulations, we develop and validate a complete compact model of RTN in RRAM devices. The model accounts for the intrinsic randomness in the number of defects contributing to the RTN and their properties. Moreover, it can be readily integrated in existing RRAM device compact models, extending their capabilities. The model is implemented in Verilog-A, and its effectiveness is demonstrated by using it to design the building block of a Truly-Random Number Generator circuit exploiting the RTN randomness as an entropy source.

2017 - Combined variability/sensitivity analysis in III-V and silicon FETs for future technological nodes [Relazione in Atti di Convegno]
Zagni, Nicolo'; Puglisi, Francesco Maria; Verzellesi, Giovanni; Pavan, Paolo

In this paper, we present a combined analysis of variability and sensitivity effects on electrical characteristics of In0.53Ga0.47As and Si ultra-scaled devices with LG= 15 nm. Two different structures, namely Dual-Gate and FinFET, are analyzed for both channel materials. Variability sources considered in this work are Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body-and Gate-Line Edge Roughness (LER). Sensitivity is assessed by varying process parameters, namely gate length, channel thickness, oxide thickness, and channel doping. Results show that variability in lnGaAs is dominated by both WFF and Body-LER, whereas WFF only dominates in Si devices. Moreover, control over gate length and channel thickness in In0.53Ga0.47As technology is fundamental in order to keep variability under reasonable values, with FinFET showing slightly better results than Dual-Gate structure. Variability is a major challenge for the industrial introduction of In0.53Ga0.47As, which could limit the alleged superior performance of In0.53Ga0.47As over Si.

2017 - Modelling nanoscale n-MOSFETs with III-V compound semiconductor channels: From advanced models for band structures, electrostatics and transport to TCAD [Relazione in Atti di Convegno]
Caruso, E.; Carapezzi, S.; Visciarelli, M.; Gnani, E.; Zagni, N.; Pavan, P.; Palestri, P.; Esseni, D.; Gnudi, A.; Reggiani, S.; Puglisi, F. M.; Verzellesi, G.; Selmi, L

We review a few state of the art solutions and recent developments to model short channel III-V compound semiconductor n-MOSFETs based on full quantum transport, semiclassical multi-valley / multi-subband transport and TCAD models. The pros and cons of each, and the insights they can deliver, are illustrated with examples from recent technology developments and literature. Areas where improvements and implementations at TCAD level are most necessary are highlighted as well.

2017 - Random dopant fluctuation variability in scaled InGaAs dual-gate ultra-thin body MOSFETs: source and drain doping effect [Relazione in Atti di Convegno]
Zagni, Nicolo; Puglisi, Francesco Maria; Pavan, Paolo; Verzellesi, Giovanni

In this paper, we present simulation results on statistical variability of threshold voltage and the respective sensitivity to process variations in Dual Gate Ultra-Thin Body (DG-UTB) InGaAs nMOSFETs at two technological nodes (with physical gate length Lg = 15 nm and Lg = 10.4 nm). Particularly, we focus on the effect of Random Dopant Fluctuations (RDF) in both the channel and the source/drain regions. While the effect of other variability sources (i.e., workfunction fluctuation, WFF, and line edge roughness, LER) can be controlled by existing technological strategies, RDF can become significant due to the 'source-starvation' effect. From our analysis, we find in fact that RDF is strongly dependent on source/drain doping, while the effect due to channel doping variation is marginal. Moreover, results indicate the possibility of achieving lower RDF variability effects at very high source/ drain doping levels that are beyond the reach of current process technology. Hence, RDF can potentially become the limiting factor to the overall variability in ultra-scaled InGaAs devices due to the difficulties in achieving very high source/drain doping.

2017 - The impact of interface and border traps on current–voltage, capacitance–voltage, and split‐CV mobility measurements in InGaAs MOSFETs [Articolo su rivista]
Pavan, Paolo; Zagni, Nicolo'; Puglisi, Francesco Maria; Alian, Alireza; Thean, Aaron Voon Yew; Collaert, Nadine; Verzellesi, Giovanni

In this article, we present coupled experimental/simulated results about the influence of interface and border traps on the electrical characteristics and split-CV mobility extraction in InGaAs MOSFETs. These results show that border traps limit the maximum drain current under on-state conditions, induce a hysteresis in the quasi-static transfer characteristics, as well as affect CV measurements, inducing an increase in the accumulation capacitance even at high frequencies where trap effects are commonly assumed to be negligible. Hysteresis in the transfer characteristics can be used as a sensitive monitor of border traps, as suggested by a sensitivity analysis where either the energetic or the spatial distribution of border traps are varied. Finally, we show that mobility extraction by means of the split-CV method is affected by appreciable errors related to the spurious contributions of interface and border traps to the total gate charge, ultimately resulting in significant channel mobility underestimation. In very narrow channel devices, channel electron spilling over the InP buffer layer can also contribute to mobility measurement inaccuracy.

2017 - Threshold Voltage Statistical Variability and Its Sensitivity to Critical Geometrical Parameters in Ultrascaled InGaAs and Silicon FETs [Articolo su rivista]
Zagni, Nicolo'; Puglisi, Francesco Maria; Verzellesi, Giovanni; Pavan, Paolo

We investigate the statistical variability of the threshold voltage and its sensitivity to critical geometrical parameters in ultrascaled In0.53Ga0.47As and Si MOSFETs by means of 3-D quantum-corrected drift-diffusion simulations. Dual-gate ultrathin-body and FinFET device structures are analyzed for both channel materials. To assess the variability and sensitivity effects also from the scaling perspective, we consider devices belonging to two technological nodes with gate lengths 15 and 10.4 nm, designed according to International Technology Roadmap for Semiconductors (ITRS) specifications. Variability sources included in our analysis are random-dopant fluctuation, work-function fluctuation (WFF), as well as body- and gate-line-edge roughness (LER). Sensitivity to critical geometrical parameters is assessed by varying gate length, channel thickness, and oxide thickness. Results point out the major detrimental effect of WFF and Body-LER for InGaAs FETs, whereas WFF dominates in Si counterparts. Moreover, the sensitivity analysis shows that control over gate length and channel thickness in the InGaAs technology is fundamental in order to keep variability within tolerable values. Scaling of the InGaAs technology highlights the importance of abiding to ITRS projections regarding LER control improvement. Furthermore, a tight channel thickness control is required in ultrascaled devices due to the large sensitivity of the threshold voltage to the channel thickness combined with increased variability.

2017 - Variability and sensitivity to process parameters variations in InGaAs Dual-Gate Ultra-Thin Body MOSFETS: A scaling perspective [Relazione in Atti di Convegno]
Zagni, Nicolò; Puglisi, Francesco Maria; Verzellesi, Giovanni; Pavan, Paolo

In this work, we present a combined analysis on the statistical variability of threshold voltage, on-state current, and leakage current of III-V ultra-scaled MOSFETs. In addition, we analyze the sensitivity of threshold voltage to critical geometrical and process parameters variations (i.e, gate length, channel thickness, oxide thickness and channel doping). Our analysis verifies the scaling potential of the InGaAs Technology from the variability/sensitivity standpoint for two technologicaTnodes (Lg = 15 nm, Lg = 10.4 nm), by means of Quantum Drift-Diffusion (QDD) simulations. The structure under investigation is a template Dual-Gate Ultra-Thin Body device realized following ITRS projections. The variability sources under consideration are: Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate-Line Edge Roughness (LER). The sensitivity analysis of threshold voltage is performed by considering also the effects of statistical variability to evaluate their combined effect. The results of the statistical variability analysis highlight the importance of carefully controlling Body-LER, as forecasted in the new IRDS report. Moreover, the combined effect of variability and sensitivity to channel thickness are found to be critical to the scaling process (down to Lg =10.4 nm), as it leads to significant leakage increase or performance reduction, potentially resulting in always-on devices.

2016 - Effects of Border Traps on Transfer Curve Hysteresis and Split-CV Mobility Measurement in InGaAs Quantum-Well MOSFETs [Relazione in Atti di Convegno]
Pavan, Paolo; Zagni, Nicolo'; Puglisi, Francesco Maria; Alian, Alireza; Thean, Aaron Voon Yew; Collaert, Nadine; Verzellesi, Giovanni

In this paper we present TCAD simulation and experimental results on the influence of interface and border traps on the electrical characteristics of InGaAs quantum-well MOSFETs. These results show that border traps limit the maximum ION, induce a hysteresis in the quasi-static transfer characteristics, and markedly affect CV measurements, inducing a large increase in the accumulation capacitance even at high frequencies where trap effects are commonly assumed to be negligible. The latter effect is particularly insidious from the technologist's perspective, since it can partially compensate quantum capacitance reduction effects, leading to CV data misinterpretation. Interface traps affect mainly the subthreshold slope of IV characteristics and cause frequency dispersion under depletion conditions. Finally, we show that channel mobility extracted by means of the split-CV method is affected by spurious contributions to the gate charge related to both interface and border traps, resulting in channel mobility underestimation.