Pagina personale di ANDREA PADOVANI

INTERMECH-Centro Interd. per la Ricerca Applicata e i Servizi nel settore della Meccanica Avanzata e della Motoristica
INTERMECH Centro Interd. per la Ricerca Applicata e i Servizi nel settore della Meccanica Avanzata e della Motoristica

T. Cabout, L. Perniola, V. Jousseaume, H. Grampeix, J.F. Nodin, A. Toffoli, E. Jalaguier, E. Vianello, G. Molas, G. Reimbold, B. De Salvo, O. Pirrotta, A. Padovani, L. Larcher, T. Diokh, P. Candelier, M.Guillermet, M. Bocquet, C. Muller (9999) - Temperature impact (up to 200 °C) on performance and reliability of HfO2-based RRAMs - 5th IEEE International Memory Workshop - IEEE - Institute of Electrical and Electronics Engineers Piscataway (USA)) - pp. da 116 a 119 ISBN: 9781467361675 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

This paper provides an overview of the temperature impact (up to 200 °C) on the electrical behavior of oxide-based RRAM, during forming, low-field resistance reading, SET/RESET, disturb, data retention and endurance. . HfO2-RRAM devices (in a 1T1R configuration) integrated in an advanced 65 nm technology are studied for this aim. We show that forming operation is strongly activated in temperature (i.e. -0.5 V per hundred Celsius degree), being much less for SET and RESET voltages (i.e. < -0.05 V per hundred Celsius degree); disturb of HRS at fixed voltage showed to be independent of temperature; endurance up to 3.106 cycles, with optimized set of stress parameters showed no significant variation; data retention at 150 °C up to 68 days showed stable programming window, after different initial programming algorithms.

D. Veksler, G. Bersuker, L. Vandelli, A. Padovani, L. Larcher, A. Muraviev, B. Chakrabarti, E. Vogel, D. C. Gilmer, P. D. Kirsch (2013) - Random telegraph noise (RTN) in scaled RRAM devices - 51th IEEE International Reliability Physics Symposium - IEEE - Institute of Electrical and Electronics Engineers Piscataway (USA)) [Attività collegate alla Ricerca - Poster]
Abstract

The random telegraph noise (RTN) related read instability in resistive random access memory (RRAM) is evaluated by employing the RTN peak-to-peak (P-p) amplitude as a figure of merit (FoM). Variation of the FoM value over multiple set/reset cycles is found to follow the log-normal distribution. In HRS, P-p decreases with the reduction of the read current, which allows scaling of the RRAM operating current. The RTN effect is attributed to the mechanism of activation/deactivation of the electron traps in (in HRS) or near (in LRS) the filament that affects the current through the RRAM device.

A. Padovani, L. Larcher, P. Pavan (2013) - Compact modeling of TANOS program/erase operations for SPICE-like circuit simulations - MICROELECTRONICS JOURNAL - n. volume 44 - pp. da 50 a 57 ISSN: 0959-8324 [Pubblicazione in Rivista - Articolo su rivista]
Abstract

We present an analytical model of TANOS program/erase transients that can be used to implement a compact SPICE-like model of these memory devices. Simulation results obtained from a physics-based TANOS model are used to derive simple analytical formulas relating the program/erase currents and the centroid of the trapped charge distribution to operating conditions and stack composition. The model allows reproducing with a good agreement the experimental program/erase transients, thus providing a valuable tool for IC designers to optimize TANOS memory circuits, especially in the framework of multi-level applications.

Andrea Padovani, Luca Larcher, Gennadi Bersuker, Paolo Pavan (2013) - Charge Transport and Degradation in HfO2 and HfOx Dielectrics - IEEE ELECTRON DEVICE LETTERS - n. volume 34 - pp. da 680 a 682 ISSN: 0741-3106 [Pubblicazione in Rivista - Articolo su rivista]
Abstract

We combine experiments and simulations to investigate leakage current and breakdown (BD) in stoichiometric and sub-stoichiometric hafnium oxides. Using charge-transport simulations based on phonon-assisted carrier tunneling between trap sites, we demonstrate that higher currents generally observed in HfOx are due to a higher density of the as-grown oxygen vacancy defects assisting the charge transport. Reduction of the dielectric breakdown field (EBD) in HfOx is explained by the lower zero-field activation energy (EA,G) of the defect generation process, as extracted from time-dependent dielectric breakdown experiments.

F. M. Puglisi, L. Larcher, G. Bersuker, A. Padovani, P. Pavan (2013) - An Empirical Model for RRAM Resistance in Low- and High-Resistance State - IEEE ELECTRON DEVICE LETTERS - n. volume 34 - pp. da 387 a 389 ISSN: 0741-3106 [Pubblicazione in Rivista - Articolo su rivista]
Abstract

We present a simple empirical expression describing hafnium-based RRAM resistance at different reset voltages and current compliances. The model that we propose describes filament resistance measured at low (~0.1 V) reading voltage in both low-resistance state (LRS) and high-resistance state (HRS). The proposed description confirms that conduction in LRS is ohmic (after forming with a sufficiently high current compliance) and is consistent with the earlier description of HRS resistance as controlled by a trap-assisted electron transfer via traps in the oxidized portion of the filament. The length of the nonohmic part of the filament is found to be directly proportional to reset voltage. Moreover, low-frequency noise measurements at different reset voltages evidence a tradeoff between HRS resistance and noise in reading conditions.

F. M. Puglisi, P. Pavan, A. Padovani, L. Larcher, G. Bersuker (2013) - RTS Noise Characterization of HfOx RRAM in High Resistive State - SOLID-STATE ELECTRONICS - n. volume 84 - pp. da 160 a 166 ISSN: 0038-1101 [Pubblicazione in Rivista - Articolo su rivista]
Abstract

In this paper we analyze Random Telegraph Signal (RTS) noise cand Power Spectral Density (PSD) in hafnium-based RRAMs. RTS measured in HRS exhibits fast and slow multilevel switching events. RTS characteristics are examined through novel color-coded time-lag plots and Hidden Markov Model (HMM) time-series analyses. Results are validated by comparing simulated and experimental PSD. Noise is examined at different reset conditions to provide an insight into the conduction mechanisms in HRS. Higher reset voltages are found to result in greater RTS complexity due to a larger number of active traps as confirmed by PSD.

Francesco Maria Puglisi, Paolo Pavan, Andrea Padovani, Luca Larcher (2013) - Perimeter and area current components in HfO2 and HfO2-x metal-insulator-metal capacitors - JOURNAL OF VACUUM SCIENCE & TECHNOLOGY. B - n. volume 31 [Pubblicazione in Rivista - Articolo su rivista]
Abstract

In this paper, the authors present an experimental analysis on current conduction mechanisms in high-k oxides, where two metal–insulator–metal structures with different insulators (HfO2 and HfO2-x) are considered. Current density measurements indicate the existence of a perimeter-related component in the current, sizeable in HfO2, and negligible in HfO2-x samples, which have to be taken into account for a correct analysis of the device behavior and cannot be based only on the area scaling rules. For oxide breakdown, for example, a significant contribution of the perimeter-related current component results in conservative extrapolations of breakdown voltages for scaled devices.

K. G. Young-Fisher, G. Bersuker, B. Butcher, A. Padovani, L. Larcher, D. Veksler, D. C. Gilmer (2013) - Leakage Current - Forming Voltage Relation and Oxygen Gettering in HfOx RRAM Devices - IEEE ELECTRON DEVICE LETTERS - n. volume 34 - pp. da 750 a 752 ISSN: 0741-3106 [Pubblicazione in Rivista - Articolo su rivista]
Abstract

We observe a trend between initial leakage currents in polycrystalline HfOx resisitive random access memory (RRAM) cells (before forming) and the forming voltages. This trend points to the dominant role played by conduction paths located at grain boundaries, which is promoted by the oxygen deficiency in ${rm HfO}_{rm x}$. One of these paths is then converted into the conductive filament responsible for nonvolatile resistance switching. In addition, we find that by engineering the RRAM stack, the forming voltage can be tuned-up to meet specific RRAM requirements, such as lower power and forming-less operations.

L. Vandelli, A. Padovani, L. Larcher, G. Bersuker (2013) - Microscopic Modeling of Electrical Stress -Induced Breakdown in Poly-Crystalline Hafnium Oxide Dielectrics - IEEE TRANSACTIONS ON ELECTRON DEVICES - n. volume 60 - pp. da 1754 a 1762 ISSN: 0018-9383 [Pubblicazione in Rivista - Articolo su rivista]
Abstract

We present a quantitative physical model describing degradation of poly-crystalline HfO2 dielectrics subjected to electrical stress culminating in the dielectric breakdown (BD). The model accounts for the morphology of the hafnium oxide film and considers the interaction of the injected electrons with the atomic defects supporting the charge transport to calculate the 3D power dissipation and temperature maps across the dielectric. This temperature map, along with that of the electric field, is used to self-consistently calculate the stress-induced defect generation rates in the dielectric during stress. The model quantitatively reproduces the evolution of the currents measured on HfO2 MIM capacitors during constant voltage stress, up to the onset of BD, and the dependencies of the time-dependent dielectric breakdown (TDDB) distributions on stress temperature and voltage. It represents a powerful tool for statistical reliability predictions that can be extended to other high-k materials, multilayer stacks and resistive RAM devices based on transition metal oxides.

B. Butcher, G. Bersuker, L. Vandelli, A. Padovani, L. Larcher, A. Kalantarian, R. Geer, D.C. Gilmer (2013) - Modeling the Effects of Different Forming Conditions on RRAM Conductive Filament Stability - 2013 5th IEEE International Memory Workshop - IEEE - Institute of Electrical and Electronics Engineers Piscataway (USA)) - pp. da 52 a 55 ISBN: 9781467361675 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In order to identify the factors controlling the filament characteristics, we perform physics-based simulations of the inherently stochastic and difficult-to-control forming process using a statistical Monte-Carlo method to model the Hf-O bond-breakage, oxygen ion diffusion and vacancy-oxygen recombination. Simulation results well reproduce the experimental trends observed for the conductivity of the post-forming low resistance state under different forming conditions. It is shown that the distribution of the oxygen ions in the surrounding oxide during forming as well as local filament temperature and electrical field all affect the filament stability.

B. Traore, K.-H. Xue, E. Vianello, G. Molas, A. Padovani, O. Pirrotta, L. Larcher, P. Blaise, L. Fonseca, B. De Salvo, Y. Nishi (2013) - Investigation of the role of electrodes on the retention performance of HfOx based RRAM cells by experiments, atomistic simulations and device physical modeling - 51th IEEE International Reliability Physics Symposium - IEEE - Institute of Electrical and Electronics Engineers Piscataway (USA)) [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this work we investigate in detail the effects of metal electrodes on the retention performances of HfOx RRAM devices. Motivated by our experimental data, we employ physics-based RRAM modeling and first-principles calculations to show that during the ON-state the concentration of oxygen interstitial (Oi) ions in the oxide depends significantly on the metal electrodes, being much larger for RRAM devices with Pt electrodes compared with Ti. The lower Oi concentration in HfOx with Ti electrodes, known as a strong oxygen getter material, results in improved retention and thermal stability. The presence of oxygen deficient conductive filaments explains the data.

F. M. Puglisi, P. Pavan, A. Padovani, L. Larcher (2013) - A Compact Model of Hafnium-Oxide-Based Resistive Random Access Memory - International Conference on IC Design and Technology - IEEE - Institute of Electrical and Electronics Engineers Piscataway (USA)) - pp. da 85 a 88 ISBN: 9781467347433 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this paper, a compact model of hafnium-oxide-based resistive random access memory (RRAM) cell is developed. The proposed model includes the effect of the temperature and cycle-to-cycle stochastic variations affecting the device operations. Simple I-V measurements are used to extract the model parameters. The model accurately reproduces the I-V curves of the switching cycles in different operating conditions.

N. Raghavan, A. Padovani, X. Wu, K. Shubhakar, M. Bosman, L. Larcher, K.L. Pey (2013) - The "Buffering" Role of High-k in Post Breakdown Degradation Immunity of Advanced Dual Layer Dielectric Gate Stacks - 51th IEEE International Reliability Physics Symposium - IEEE - Institute of Electrical and Electronics Engineers Piscataway (USA)) [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

Post breakdown (BD) reliability is an important area of study in ultra-thin gate dielectrics as it has significant implications on the performance degradation, lifetime, reliability margin and power dissipation of advanced sub-22 nm transistors and circuits. A prolonged phase of post-BD can ensure we can live with the circuit with moderate performance and error-free operation, even if the soft breakdown (SBD) events occur early. While analysis of post-BD is simple and straightforward for single layer SiO2 / SiON stacks, the number of possible scenarios of post-BD increases when analyzing high-? – interfacial layer (HK-IL) based technology. This is because the sequence of BD (whether HK or IL fails first followed by the other one) and the competition between multiple SBD in one of these layers, dilative wear-out of a single SBD spot and the possibility of a successive localized BD above / below the HK/IL BD percolation spot (with or without metal filamentation) are all possible phenomena that can be classified as post-BD. The likelihood of occurrence of these various possibilities will determine the immunity of the stack to post-BD degradation. We will investigate each of these scenarios in detail in this work in order to provide a comprehensive assessment of post-BD reliability of state-of-the-art technology. Our analysis on a HK:IL = 25:12? stack supported by electrical, physical and modeling results provides clear evidence that circuit failure at operating conditions can only be due to multiple SBD events within the IL layer and that the HK is very robust and resilient to breakdown.

A. Padovani, A. Arreghini, L. Vandelli, L. Larcher, G. Van den bosch, J. Van Houdt (2012) - Evidences for vertical charge dipole formation in charge-trapping memories and its impact on reliability - APPLIED PHYSICS LETTERS - n. volume 101 - pp. da 0535 a 0535 ISSN: 0003-6951 [Pubblicazione in Rivista - Articolo su rivista]
Abstract

We demonstrate the formation of a vertical charge dipole in the nitride layer of TaN/Al2O3/Si3N4/SiO2/Si memories and use dedicated experiments and device simulations to investigate its dependence on program and erase conditions. We show that the polarity of the dipole depends on the program/erase operation sequence and demonstrate that is at the origin of the charge losses observed during retention. This dipole severely affects the retention of mildly programmed and erased states, representing a serious reliability concern especially for multi-level applications.

S. Cimino, A. Padovani, L. Larcher, V.V. Afanas’ev, H.J. Hwang, Y.G. Lee, M. Jurczac, D. Wouters, B.H. Lee, H. Hwang, L. Pantisano (2012) - A study of the leakage current in TiN/HfO2/TiN capacitors - MICROELECTRONIC ENGINEERING - n. volume 95 - pp. da 71 a 73 ISSN: 0167-9317 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

Physical and electrical characteristics of Metal–Insulator–Metal TiN/HfO2/TiN capacitors have been investigated. A detailed study using internal photoemission and trap assisted transport simulation enabled the extraction of relevant important parameters like barrier height (2.5 eV) for both injecting interfaces, optical energy gap (5.6 eV), as well as trap density and energy position within the bandgap (NT = 3E19 cm-3; rT = 1E14 cm2; ET = 2.0–2.6 eV below the bottom of the HfO2 conduction band). The extracted parameters surprisingly showed striking similarities with HfO2 deposited on a Si surface, i.e., in MOSFET process flow. Additionally, Constant Voltage Stress showed a leakage current increase, preferentially at low voltage. This can be explained by preexisting defect precursors (likely related to oxygen vacancies) or by involvement of hydrogen in creating defects as observed on thermal SiO2 layers.

A. Kalantarian, G. Bersuker, D. C. Gilmer, D. Veksler, B. Butcher, A. Padovani, O. Pirrotta, L. Larcher, P. Kirsch, Y. Nishi (2012) - Controlling Uniformity of RRAM Characteristics via the Forming Process - IEEE International Reliability Physics Symposium - IEEE Piscataway (USA)) [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

The proposed constant voltage forming (CVF) is shown to increase the resistances of the low resistance and high resistance states while reducing their variability. By forcing the forming in all devices to occur at the same predefined voltage,the CVF method eliminates a major cause of the device-to-device variation associated with the randomness of the forming voltage values. Moreover,both experiments and simulations show that CVF at lower voltages suppresses the parasitic overshoot current,resulting in a more controlled and smaller filament cross-section and lower operation currents.

A. Padovani, L. Larcher, P. Pavan, C. Cagli, B. de Salvo (2012) - Understanding the Role of the Ti Metal Electrode on the Forming of HfO2-based RRAMs - 2012 4th IEEE International Memory Workshop - IEEE Piscataway (USA)) - pp. da 127 a 130 ISBN: 9781467310802 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this paper we investigate in details the effects of the Ti metal electrode on the forming operation in HfO2 RRAM devices. Starting from electrical data and physico-chemical analysis, we use physics-based RRAM modeling to understand the physics governing the CF formation in RRAM stacks with Ti electrodes. Simulations show that the lower forming voltage typically observed in these devices is due to the Ti-induced formation of a sub-stoichiometric HfOx region in the resistive switching layer. The model allows extracting the characteristics of this sub-stoichiometric region that are crucial for developing future low-voltage RRAM devices.

C. D. Young, G. Bersuker, M. Jo, K. Matthews, J. Huang, S. Deora, K.-W. Ang, T. Ngai, A. Padovani, L. Larcher, Chris Hobbs, P.D. Kirsch (2012) - New Insights into SILC Monitoring During TDDB Stress - IEEE International Reliability Physics Symposium - IEEE Piscataway (USA)) [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

The breakdown (TDDB/SILC) characteristics of nMOS transistors with hafnium-based gate dielectric stacks of various zirconium content were investigated. It is found that the gate stack composition affects the SILC-voltage dependency while the voltage value chosen for SILC monitoring impacts significantly the SILC-based lifetime projection. For the worst case lifetime evaluation, SILC should be monitored at its maximum value rather than at any pre-defined, fixed voltage.

F.M. Puglisi, P. Pavan, A. Padovani, L. Larcher, G. Bersuker (2012) - Random Telegraph Signal Noise Properties of HfOx RRAM in High Resistive States - Proceedings of the 42nd European Solid-State Device Research Conference - IEEE - Institute of Electrical and Electronics Engineers Piscataway, NJ (USA)) - pp. da 274 a 277 ISBN: 9781467330862 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this paper we analyze Random Telegraph Signal (RTS) noise in hafnium-based RRAMs. RTS is measured in HRS, showing fast and slow multilevel switching events. RTS characteristics are examined through novel color-coded time-lag plots and Hidden Markov Model (HMM) time-series analyses. Noise is examined at different reset conditions to provide new insights on conduction mechanisms in HRS. Higher reset voltages result in an enhanced complexity in RTS due to a larger number of active traps

G. Broglia, M. Montorsi, L. Larcher, A. Padovani (2012) - DENSITY INFLUENCE ON AMORPHOUS HFO2 STRUCTURE: A MOLECULAR DYNAMICS STUDY - Frontiers in Electronic Materials - wiley-vch germania (DEU)) - pp. da 495 a 496 ISBN: 9783527411917 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this scenario, the aim of this work is to analyse systematically the influence of the material density on the structure of amorphous HfO2 (a-HfO2). We will focus on investigating the atomic structure in the short, medium and long range in order to understand which is the preferential atomic structure. The molecular dynamics technique has been chosen for this analysis because it permits to investigate accurately the short and medium structural order of this material.

L. Larcher, A. Padovani, O. Pirrotta, L. Vandelli, G. Bersuker (2012) - Microscopic understanding and modeling of HfO2 RRAM device physics - 2012 International Electron Devices Meeting TECHNICAL DIGEST - IEEE - Institute of Electrical and Electronics Engineers Piscataway (USA)) - pp. da 474 a 477 ISBN: 9781467348706 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this paper we investigate the physical mechanisms governing operations in HfOx RRAM devices. Forming set and reset processes are studied using a model including power dissipation associated with the charge transport, and the corresponding temperature increase, which assists ion diffusion.

L. Larcher, A. Padovani, P. Pavan (2012) - Leakage current in HfO2 stacks: from physical to compact modeling - Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - NSTI Cambridge, Massachusetts, USA (USA)) - pp. da 809 a 814 ISBN: 9781466562752 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this paper we discuss the physical mechanisms governing the charge transport inside hafnium based dielectric stack from a modeling perspective. We propose a detailed Monte-Carlo physical model, which describes the charge transport across high-k stacks through the multiphonon trap-assisted-tunneling theory. This model reproduces accurately the voltage and temperature dependencies of the leakage current across HfO2-based stacks. Starting from this physical description, we develop an analytical model for the TAT current across high-k stacks, which can be implemented into SPICE-like circuit simulators. Despite the simplifying approximations, this compact model reproduces accurately the measurements, thus representing an effective tool for the investigation of the TAT currents.

A. Padovani, A. Arreghini, L. Vandelli, L. Larcher, G. Van den Bosh, P. Pavan, J. Van Houdt (2011) - A Comprehensive Understanding of the Erase of TANOS Memories Through Charge Separation Experiments and Simulations - IEEE TRANSACTIONS ON ELECTRON DEVICES - n. volume 59 - pp. da 3147 a 3155 ISSN: 0018-9383 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

We investigate and quantify the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations. Results demonstrate that electron emission via trap to-band tunneling dominates the first part of the erase operation, whereas hole injection prevails in the remaining part of the transient. In addition, we show that the efficiency of the erase operation is high and constant mainly because of the high energy offset between nitride and alumina valence bands. Our results clearly identify the physical mechanisms responsible for TANOS erase and allow deriving some important guidelines for the optimization of this operation.

A. Padovani, L. Larcher, V. Della Marca, P. Pavan, H. Park, G. Bersuker (2011) - Charge trapping in alumina and its impact on the operation of metal-alumina-nitride-oxide-silicon memories: experiments and simulations - JOURNAL OF APPLIED PHYSICS - n. volume 110 - pp. da 0145 a 0145 ISSN: 0021-8979 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

We investigate electron/hole trapping phenomena in alumina blocking oxide and their impact on the program/erase operations and retention of TANOS memory devices. For this purpose, we perform simulations using a physical model reproducing charge injection/trapping in TANOS devices, which is extended to account for the charge trapping phenomena in the blocking layer. We derive the electrical characteristics of both electron and hole traps in Al2O3 by reproducing the measured program, erase and retention transients. Our results show that the amount of electron charge trapped in the alumina during a program operation strongly depends on the stack composition and program voltages and can account for up to 25% of the total threshold voltage shift, whereas hole trapping during erase is negligible. Finally, we investigate the degradation of retention caused by the electron trapping in the alumina blocking layer, which is shown to result in accelerated charge loss.

G. Bersuker, D. C. Gilmer, D. Veksler, P. Kirsch, L. Vandelli, A. Padovani, L. Larcher, K. McKenna, A. Shluger, V. Iglesias, M. Porti, and M. Nafría (2011) - Metal oxide resistive memory switching mechanism based on conductive filament properties - JOURNAL OF APPLIED PHYSICS - n. volume 110 - pp. da 1245 a 1245 ISSN: 0021-8979 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament (CF) features controlling TiN/HfO2/TiN resistive memory operations. The leakage current through the dielectric is found to be supported by the oxygen vacancies, which tend to segregate at hafnia grain boundaries. We simulate the evolution of a current path during the forming operation employing the multi-phonon trap-assisted tunneling (TAT) electron transport model. The forming process is analyzed within the concept of dielectric breakdown, which exhibits much shorter characteristic times than that of the electroforming process conventionally employed to describe the formation of the conductive filament. The resulting conductive filament is calculated to produce a non-uniform temperature profile along its length during the reset operation, promoting preferential oxidation of the filament tip. A thin dielectric barrier resulting from the CF tip oxidation is found to control filament resistance in the high resistance state. Field-driven dielectric breakdown of this barrier during the set operation restores the filament to its initial low resistive state. These findings point to the critical importance of controlling the filament resistance characteristics (cross section, stoichiometry) during forming to achieve low power RRAM cell switching.

G. Bersuker, D. Veksler, C. D. Young, H. Park W. Taylor, P. Kirsch, R. Jammy, L. Morassi, A. Padovani, L. Larcher (2011) - Connecting electrical and structural dielectric characteristics - INTERNATIONAL JOURNAL OF HIGH SPEED ELECTRONICS AND SYSTEMS - n. volume 20 - pp. da 65 a 79 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

An attempt is made to correlate electrical measurement results to specific defects in the dielectric stacks of high-k/metal gate devices. Defect characteristics extracted from electrical data were compared to those obtained by ab initio calculations of the dielectric structures. It is demonstrated that oxygen vacancies in a variety of charge states and configurations in the interfacial SiO2 layer of the high-k gate stacks contribute to random telegraph noise signal, time-dependent dielectric breakdown, and the flatband voltage roll-off phenomenon.

G. Bersuker, J. Yum, L. Vandelli, A. Padovani, L. Larcher, V. Iglesias, M. Porti, M. Nafría, K. McKenna, A. Shluger, P. Kirsch, R. Jammy (2011) - Grain boundary-driven leakage path formation in HfO2 dielectrics - SOLID-STATE ELECTRONICS - n. volume 65-66 - pp. da 146 a 150 ISSN: 0038-1101 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

The evolution over time of the leakage current in HfO2-based MIM capacitors under continuous or periodic constant voltage stress (CVS) was studied for a range of stress voltages and temperatures. The data were analyzed based on the results of conductive atomic force microscopy (AFM) measurements demonstrating preferential current flow along grain boundaries (GBs) in the HfO2 dielectric and ab initio calculations, which show the formation of a conductive sub-band due to the precipitation of oxygen vacancies at the GBs. The simulations using the statistical multi-phonon trap-assisted tunneling (TAT) current description successfully reproduced the experimental leakage current stress time dependency by using the calculated energy characteristics of the O-vacancies. The proposed model suggests that the observed reversible increase in the stress current is caused by segregation of the oxygen vacancies at the GBs and their conversion to the TAT-active charge state caused by reversible electron trapping during CVS.

L. Larcher, A. Padovani, L. Vandelli, G. Bersuker (2011) - (Invited) Physical Modeling of Charge Transport and Degradation in HfO2 Stacks for Logic Device and Memory Applications - ECS TRANSACTIONS - n. volume 37 - pp. da 189 a 197 ISSN: 1938-5862 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

The understanding of the physical mechanisms responsible of charge transport and degradation in high-k stacks is fundamental for the optimization of advanced logic (MOSFETs) and memory (RRAM, DRAM) devices. In this paper, we present a comprehensive physical model describing the charge transport and the degradation/breakdown processes in the HfO2 layer. This model allows gaining quantitative insights into the physics governing leakage current and degradation processes in HfO2 stacks, reproducing gate current and TDDB statistics

L. Larcher, A. Padovani, L. Vandelli, P. Pavan (2011) - Charge transport in high-k stacks for charge-trapping memory applications: A modeling perspective (invited) - MICROELECTRONIC ENGINEERING - n. volume 88 - pp. da 1168 a 1173 ISSN: 0167-9317 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

Charge trapping (CT) memories could be a promising technology option for further NAND Flash scaling. The assessment of the scalability limits and ultimate performances of this technology demands for the comprehensive understanding of the physical mechanisms governing device operation and reliability, which requires accurate physics-based models reproducing the electrical device characteristics. The basic features of the models presented in the literature for CT memory devices are reviewed, underlining their similarities and differences, and highlighting their importance in order to achieve a comprehensive understanding of the physical mechanisms responsible for CT device operation and reliability. A physical model describing the charge transport in nitride and high-j stacks is also presented, which allows gaining further insights into reliability issues related to charge localization and high-j tunnel and blocking dielectrics, like the effects of the blocking alumina layer and the band-gap engineered tunnel dielectrics on the TANOS device retention.

L. Morassi, A. Padovani, G. Verzellesi, D. Veksler, I. Ok, G. Bersuker (2011) - Interface-trap effects in inversion-type enhancement-mode InGaAs/ZrO2 n-channel MOSFETs - IEEE TRANSACTIONS ON ELECTRON DEVICES - n. volume 58 - pp. da 107 a 114 ISSN: 0018-9383 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

Interface-trap effects are analyzed in inversion-type enhancement-mode In0.53Ga0.47As/ZrO2 and In0.53Ga0.47As/In0.2Ga0.8As/ZrO2 n-channel MOSFETs by comparing the measurements and the numerical device simulations of dc transfer characteristics. Device simulations can reproduce measured threshold voltages under the hypothesis that interface traps are donorlike throughout the InGaAs band gap, allowing for strong inversion operation regardless of the relatively high interface-trap density. The effects induced by the donorlike interface traps in MOSFETs having a thin In0.2Ga0.8As cap layer interposed between gate dielectric and channel are qualitatively different from those observed in standard MOSFETs (without the cap). Increasing the donorlike trap density decreases the threshold voltage in capped devices, whereas it leaves it unchanged in uncapped ones. As a result, donorlike interface traps can explain the threshold-voltage difference observed in MOSFETs with and without the cap.

L. Vandelli, A. Padovani, L. Larcher, R.G. Southwick III, W.B. Knowlton, G. Bersuker (2011) - A Physical model of the temperature dependence of the current through SiO2/HfO2 stacks - IEEE TRANSACTIONS ON ELECTRON DEVICES - n. volume 59 - pp. da 2878 a 2887 ISSN: 0018-9383 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

In this paper, we investigate the characteristics of the defects responsible for the leakage current in the SiO2 and SiO2/HfO2 gate dielectric stacks in a wide temperature range (6 K–400 K). We simulated the temperature dependence of the I–V characteristics both at positive and negative gate voltages by applying the multiphonon trap-assisted tunneling model describing the charge transport through the dielectric. In the depletion/weak inversion regime, the current is limited by the supply of carriers available for tunneling. In strong inversion, the temperature dependence is governed by the charge transport mechanisms through the stacks; in particular, in SiO2/HfO2 dielectric stacks, the coupling of the injected carriers with the dielectric phonons at the trap sites is the dominant mechanism.Matching the simulation results to the measurement data allows extracting important trap parameters, e.g., the trap relaxation and ionization energies, which identify the atomic structure of the electrically active defects in the gate dielectric.

W.H. Liu, K.L. Pey, X. Wu, N. Raghavan, A. Padovani, L. Larcher, L. Vandelli, M. Bosman, T. Kauerauf (2011) - Threshold Shift Observed in Resistive Switching in Metal-Oxide-Semiconductor Transistors and the Effect of Forming Gas Anneal - APPLIED PHYSICS LETTERS - n. volume 99 - pp. da 2329 a 2329 ISSN: 0003-6951 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

In this paper the resistive switching mechanism, which is crucial for the operations of RRAM devices, is investigated using HfO2 based MOSFETs. After the SET operation, MOSFETs exhibit a threshold voltage (VT) shift that is found to be closely related to the formation of conductive filaments in the gate oxide. The RESET operation performed through a forming gas anneal treatment is found to have the same effect of applying a reverse polarity gate voltage sweep, as usually done in bipolar switching RRAM devices. After RESET, the gate current and VT measured shift back to their pristine levels, indicating the passivation of oxygen vacancies (forming the conductive path) as the most likely physical mechanism responsible for RRAM’s RESET operation. TEM analysis and physical simulations support these conclusions.

A. Kalantarian, G. Bersuker, D.C. Gilmer, B. Butcher, A. Padovani, L. Vandelli, L. Larcher, R. Geer, Y. Nishi, P. Kirsch (2011) - Low Power RRAM with Improved HRS/LRS Uniformity through Efficient Filament Control Using CVS Forming (unknown - Abstracts of the 42nd IEEE Semiconductor Interface Specialists Conference - unknown unknown (USA)) - n. volume 1 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

Resistance change memory (RRAM) based on transition metal oxides (TMO), whose operation is based on the change in resistivity of a conductive filament in the oxide material, has attracted a lot of attention in recent years due to its promise of high density, speed, and retention. However, achieving a low power operation and high device-to-device uniformity of the cell resistance states are the major challenges for practical applications of the RRAM technology. While some progress has been made on the understanding of the switching mechanism of TMO memory devices [1], lack of precise control over the filament formation, perceived to be a random process, which inturn introduces randomness into the switching characteristics ofthis class of devices, complicates further progress. This studydemonstrates a forming methodology, which addresses the abovediscussed issues by performing a forming operation under theconstant voltage stress (CVS) condition at lower voltages ratherthan by the conventionally used fast voltage ramp method. Thisapproach is shown to lower the reset current, increase resistivityof the low and high resistive states (LRS, HRS) and improvedevice to device uniformity in the HfO2-based RRAM devices.

A. Padovani, L. Larcher, L. Vandelli, O. Pirrotta, P. Pavan (2011) - Modeling the Charge Transport and Degradation in HfO2 Dielectric for Reliability Improvement and Life-Time Predictions in Logic and Memory Devices (unknown - Technical Proceedings of the 2011 International Semiconductor Device Research Symposium - unknown unknown (USA)) - n. volume 1 - pp. da 1 a 2 ISBN: 9781457717543 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

HfO2 is currently used in the gate stacks of CMOS logic devices and is widely investigated for its potential application in advanced non-volatile memories such as resistive switching devices (RRAMs). In both applications, the understanding of the physical mechanisms governing the charge transport and the degradation/breakdown (BD) of the dielectric is fundamental to optimize device operation and reliability, and represents the first step toward accurate lifetime predictions. These goals can be achieved through the development of accurate physics-based models linking the microscopic properties of HfO2 to the electrical behavior of the device. We show the model we developed for the charge transport and degradation in HfO2 and its application to logic and memory devices.

A. Padovani, L. Larcher, P. Pavan (2011) - Modeling strategies for flash memory devices (unknown - Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011 - unknown unknown (USA)) - n. volume 2 - pp. da 762 a 767 ISBN: 9781439871393 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this paper, we will review the modeling strategies for standard and advanced Flash memory devices based on Floating Gate devices developed by our research group in the last ten years. We will show a complete compact model that includes program/erase and leakage currents that can be used to simulate memory cells in both DC (read operation) and transient conditions (Program/Erase). The same model can be used also for reliability simulations by providing good descriptions of the degradation mechanisms. We will also show the extended model for circuit simulation of NAND strings, modified to account for capacitive coupling effects. Finally, we will show how the same framework can be used to develop a compact model for operations of advanced planar charge-trapping memory devices.

C. Cagli, J. Buckley, V. Jousseaume, A. Salaun, H. Grampeix, J. F. Nodin, H. Feldis, A. Persico, J. Cluzel, P. Lorenzi, L. Massari, R. Rao, F. Irrera, T. Cabout, F. Aussenac, C. Carabasse, M. Coue, P. Calka, E. Martinez, L. Perniola, P. Blaise, Z.Fang, Y. H. Yu, G. Ghibaudo, D. Deleruyelle, M. Bocquet, C. Muller, A. Padovani, O. Pirrotta, L. Vandelli, L. Larcher, G. Reimbold, B. de Salvo (2011) - Experimental and Theoretical Study of Electrode Effects in HfO2 based RRAM - Proc. IEDM - IEEE Piscataway (USA)) - n. volume 1 - pp. da 28.7 a 28.7 ISBN: 9781457705052 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this work, the impact of Ti electrodes on the electrical behaviour of HfO2-based RRAM devices is conclusively clarified. To this aim, devices with Pt, TiN and Ti electrodes have been fabricated. We first provide several experiments to clearly demonstrate that switching is driven by creation-disruption of a conductive filament. Thus, the role of TiN/Ti electrodes is explained and modeled based on the presence of HfOx interfacial layer underneath the electrode. In addition, Ti is found responsible to activate bipolar switching. Moreover, it strongly reduces forming and switching voltages with respect to Pt-Pt devices. Finally, it positively impacts on retention. To support and interpret our results we provide physico-chemical measurements, electrical characterization, ab-initio calculations and modeling.

L. Vandelli, A. Padovani, L. Larcher, G. Bersuker, D. Gilmer, P. Pavan (2011) - Modeling of the forming operation in HfO2-base resistive switching memories - 3rd IEEE International Memory Workshop - IEEE Piscataway (USA)) - pp. da 119 a 122 ISBN: 9781457702259 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

This paper presents a novel physical description of the forming process in HfO2-based resistive switching memory devices (RRAM). By taking into consideration a grain boundary-driven trap-assisted electron transport and accounting for the local power dissipation and the associated local temperature increase, which assists defect generation, the model reproduces quantitatively the evolution of the leakage current observed during the forming operation in the RRAM devices. The model statistical capabilities allow reproducing the statistical distribution of the forming voltage, thus providing a powerful tool for the assessment of the feasibility of these devices for high-capacity non-volatile memory mass storage applications

L. Vandelli, A. Padovani, L. Larcher, G. Broglia, G. Ori, M. Montorsi, G. Bersuker, P. Pavan (2011) - Comprehensive physical modeling of forming and switching operations in HfO2 RRAM devices - Proc. IEDM - IEEE unknown (USA)) - n. volume 1 - pp. da 17.5 a 17.5 ISBN: 9781457705052 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this work we apply a physical model based on charge transport and molecular mechanics/dynamics simulations to investigate the physical mechanisms governing the RRAM forming and switching operations. The proposed model identifies the major driving forces controlling conductive filament (CF) formation and changes during RRAM switching, thus providing a tool for investigation and optimization of RRAM devices.

L. Vandelli, G. Bersuker, A. Padovani, J.H. Yum, L. Larcher, P. Pavan (2011) - A Physics-Based Model of the Dielectric Breakdown in HfO2 for Statistical Reliability Prediction - IEEE International Reliability Physics Symposium - IEEE Piscataway (NJ, USA) (USA)) - pp. da 807 a 810 ISBN: 9781424491117 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

We present a quantitative physical model describing the current evolution due to the formation of a conductive filament responsible for the HfO2 dielectric breakdown. By linking the microscopic properties of the stress-generated electrical defects to the local power dissipation and to the corresponding temperature increase along the conductive path the model reproduces the rapid current increase observed during the breakdown. The model successfully simulates the experimental time-dependent dielectric breakdown distributions measured in HfO2 MIM capacitors under constant voltage stress, thus providing a statistical reliability prediction capability, which can be extended to other high-k materials, multilayer stacks, resistive memories based on transition metal oxides, etc.

L. Larcher, A. Bertacchini, A. Ricciardi, P. Pavan, A. Padovani (2010) - Models, Solutions, Methods and Tools for Energy-Aware Design [Attività collegate alla Ricerca - Partecipazione a progetti di ricerca]
Abstract

Energy efficiency is one of the most critical aspects of today’s information society. Reducing energy consumption of electronic devices, circuits and systems, paired to improving energy generation, conversion, storage and management capabilities represent the biggest challenges that engineers and scientists operating in the electronics sector will have to face in the next decade. Solid-state devices, integrated circuits and systems based on these devices, have an increasingly pivotal role in all steps of the energy production and management pipeline. Advances in electronics have made it possible to increase the intelligence” of energy generation, conversion, distribution: we are now entering the era of smart power grids, smart energy consumption metering and monitoring, smart energy conversion ([1],[2],[3]). In these contexts, the term “smart” implies awareness of environmental conditions, coupled with the capability of suitably adapting system behaviour without direct and continuous human intervention. For instance, photovoltaic energy conversion can greatly benefit from adaptation to solar irradiation of the panel operating points, to maintain maximum power transfer from the PV panels to the electric plants under a wide variety of environmental conditions. Clearly, the cost of intelligence must be much lower than the advantages it brings in terms of increased efficiency, responsiveness, robustness. This implies non-trivial design choices and tradeoffs, which can be explored only with adequate design automation support. For instance, maximum power point tracking (MPPT) solutions are justified only when they produce an increase in the energy collected by a PV panel significantly greater than the energy they consume to monitor solar irradiation and to compute optimal panel operating point [4]. Quantitatively determining if an MPPT solution has a positive energy balance requires accurate modelling not only of the PV panel itself, but also of the energy conversion circuits and the mixed-signal circuits that monitor power transfer and compute the optimal panel operating point. Robust and accurate modelling is only a facet of the problem: computer-aided design exploration/optimization is another, equally-important aspect, as the complexity of design solutions is such that manual exploration would be too slow, error-prone and expensive. The END project targets the development of innovative energy-aware design solutions and EDA technologies for next generations’ nanoelectronics circuits and systems, and the related energy generation, conversion and management systems. The ultimate objective of the END project is that of bringing such solutions and technologies into the product development processes of the industrial partners of the Consortium, thus enabling the design and manufacturing of the electronic circuits that will be at the basis of the green information society of the future. It is important to stress the fact that minimizing the power consumption of electronic devices and circuits themselves is only a partial objective, which may not coincide with the overreaching goal of increasing the energy efficiency of systems and systems-of-systems where electronics plays the role of critical enablers. These complex systems generally include energy conversion and storage sub-systems where a marginal efficiency increase may be more than sufficient to justify a power budget to operate electronic devices that make it possible. In the past these sub-systems were designed in isolation and interfaced as commercial-off-theshelf components, relying on human ingenuity and intuition to obtain efficient, if not optimal solutions. The END project will pursue the energy efficiency objective through an innovative holistic approach, which combines research work in modelling, design and EDA technologies with strategic application drivers, which will serve both for requirement setting and concept demonstration. Distinguishing feature of the

A. Padovani, L. Larcher, D. Heh, G. Bersuker, V. Dellamarca, P. Pavan (2010) - Temperature Effects on Metal-Alumina-Nitride-Oxide-Silicon Memory Operations - APPLIED PHYSICS LETTERS - n. volume 96 - pp. da 2235 a 2235 ISSN: 0003-6951 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

We present a detailed investigation of temperature effects on the operation of TaN/Al2O3 / Si3N4 /SiO2 / Si (TANOS) memory devices. We show that not only retention but also program and erase operations are affected significantly by temperature. Using a large set of experimental data and simulations on a variety of TANOS stacks, we show that the temperature dependence of TANOS program and erase operations can be explained by accounting for that the alumina dielectric constant increases by 20%–25% over a 125 K temperature range.

A. Padovani, L. Morassi, N. Raghavan, L. Larcher, L. Wenhu, K. L. Pey, G. Bersuker (2010) - A Physical Model for Post-Breakdown Digital Gate Current Noise - IEEE ELECTRON DEVICE LETTERS - n. volume 31 - pp. da 1032 a 1034 ISSN: 0741-3106 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

We present a new physical model that enables us to reproduce the digital gate current Random Telegraph Noise (RTN) fluctuations observed in ultra-thin SiON dielectrics in the early stages of post breakdown (BD). Gate current (IG) fluctuations are modeled assuming that some traps in the BD path switch between two unstable configurations, corresponding to neutral and negatively charged O vacancies. Energy levels of the trap considered in simulations here are consistent with values calculated from atomistic simulations. The model allows to reproduce accurately the mean and variation in the IG fluctuations observed on 16Å and 22Å thick SiON gate dielectric at different gate voltages.

A. Suhane, A. Arreghini, G. Van den bosch, L. Vandelli, A. Padovani, L. Breuil, L. Larcher, K. De Meyer, J. Van Houdt (2010) - Experimental assessment of electrons and holes in erase transient of TANOS and TANVaS memories - IEEE ELECTRON DEVICE LETTERS - n. volume 31 - pp. da 936 a 938 ISSN: 0741-3106 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

We present carrier separation experiments based on direct charge measurement to assess the contributions of electrons and holes to the erase transient of TANOS-like nonvolatile memories. The role of the different carrier species is analyzed as a function of the erase voltage and of the charge configuration at the initial programmed state. We extend the analysis to Band Engineered tunneling barriers, demonstrating that the performance improvement in these devices lays more in an enhancement of the hole current rather than of the electron one.

L. Larcher, A. Padovani (2010) - High-k related reliability issues in advanced Non-Volatile Memories - MICROELECTRONICS RELIABILITY - n. volume 50 - pp. da 1251 a 1258 ISSN: 0026-2714 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

In the last decade, important technology solutions have been proposed to scale down Flash memory devices beyond the 30 nm node. The most important innovations are the introduction of charge trapping layer and high-j materials in both bottom and top dielectric stacks. Such innovations allow reducing both the bottom dielectric thickness and the Program/Erase (P/E) voltages, while maintaining the P/E performances without degrading (theoretically) the memory device reliability. Theoretical advantages and reliability issues of these important innovations will be reviewed by addressing physical mechanisms responsible of reliability degradation. In particular, the reliability consequences of the discrete charge storage and of the high-j band-gap engineered barriers bottom and top dielectric stacks will be carefully analyzed, relating high-j material properties to memory device performances and reliability.

S. Cimino, A. Padovani, L. Larcher, V.V. Afanas’ev, H. J. Hwang, Y. G. Lee, M. Jurczac, D. Wouters, B.H. Lee, H. Hwang, L. Pantisano (2010) - Leakage current in TiN/HfO2/TiN MIM capacitors and degradation due to electrical stress - ECS TRANSACTIONS - n. volume 33 - pp. da 537 a 543 ISSN: 1938-5862 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

Electrical characteristics of TiN/HfO2/TiN capacitors have been investigated by means of leakage current and Random Telegraph Noise measurements. Trap assisted transport simulation allowed the extraction of relevant parameters like trap density and trap energy position. The extracted parameters show striking similarities with those reported for HfO2 deposited on a Si surface (i.e., MOSFET applications). Additionally, even low bias Constant Voltage Stress was found to induce leakage current degradation on current vs voltage characteristics, preferentially at low voltage. The leakage current degradation is explained by preexisting defect precursors or by involvement of hydrogen in creating defects as observed on thermal SiO2 layers.

L. Larcher, A. Padovani (2010) - High-k related reliability issues in advanced Non-Volatile Memories - MICROELECTRONICS RELIABILITY - n. volume 50 - pp. da 1251 a 1258 ISSN: 0026-2714 [Atto di Convegno (in Rivista) - Relazione in Rivista di Atti di Convegno]
Abstract

In the last decade, important technology solutions have been proposed to scale down Flash memory devices beyond the 30nm node. The most important innovations are the introduction of charge trapping layer and high-? materials in both bottom and top dielectric stacks, which allows reducing both the bottom dielectric thickness and the Program/Erase voltages, while maintaining the P/E performances and (theoretically) without degrading the memory device reliability. Theoretical advantages and reliability issues of these important innovations will be reviewed by addressing physical mechanisms responsible of reliability degradation. In particular, charge trapping layers introduced in place of the poly-silicon FG will be discussed highlighting the reliability consequences of the discrete charge storage. Similarly, theoretical advantages and reliability issues of bottom and top dielectric stacks incorporating high-? materials (used mainly also to implement band-gap engineered barriers) will be carefully analyzed, relating high-? material properties to memory device performances and reliability.

L. Morassi, A. Padovani, G. Verzellesi, D. Veksler, I. Ok, G. Bersuker (2010) - Study of the impact of interface traps on the electrical characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k gate dielectrics - HETECH 2010 Book of Abstracts - FORTH Crete (GRC)) [Atto di Convegno (in Volume) - Abstract in Volume di Atti di Convegno]
Abstract

Interface-trap effects are investigated in inversion-type InGaAs/ZrO2 MOSFETs and implant-free InGaAs/Al2O3 MOSHEMTs. Specific aspects that are addressed are (i) the different impact of donor- and acceptor-like traps; (ii) the effects of interface traps in buried channel devices; (iii) the role played by the charge neutrality level at the dielectric interface.

A. Padovani, L. Larcher (2010) - A novel Algorithm for the Solution of Charge Transport Equations in MANOS Devices Including Charge Trapping in Alumina and Temperature Effects - SISPAD - IEEE Piscataway (NY, USA) (USA)) - pp. da 229 a 232 ISBN: 9781424477012 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

We present a new algorithm for the exact solution of the system of equations describing charge trapping and transport across the dielectric stack of nitridebased charge trapping memories. The algorithm is implemented in a physical MANOS model accounting for temperature effects and charge trapping into the Al2O3 blocking layer. The model reproduces threshold voltage shifts measured at different temperatures on different MANOS stacks.

G. Bersuker, D. C. Gilmer, D. Veksler, J. Yum, H. Park, S. Lian, L. Vandelli, A. Padovani, L. Larcher, K. McKenna, A. Shluger, V. Iglesias, M. Porti, M. Nafría, W. Taylor, P. D. Kirsch, R. Jammy (2010) - Metal oxide RRAM switching mechanism based on conductive filament microscopic properties - Proc. IEDM - IEEE Piscataway (NJ, USA) (USA)) - pp. da 19.6 a 19.6 ISBN: 9781442474185 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament features controlling TiN/HfO2/TiN resistive memory operations. The forming process is found to define the filament geometry, which in turn determines the temperature profile and, consequently, the switching characteristics. The findings point to the critical importance of controlling filament dimensions during the forming process (polarity, max current/voltage, etc.).

G. Bersuker, D. Heh, C. D. Young, L. Morassi, A. Padovani, L. Larcher, K. S. Yew, Y. C. Ong, D. S. Ang, K. L. Pey, W. Taylor (2010) - Mechanism of high-k dielectric-induced breakdown of interfacial SiO2 layer - Proc. of IEEE International Reliability Physics Symposium - IEEE Piscataway (NY, USA) (USA)) - pp. da 373 a 378 ISBN: 978-1-4244-5430-3 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

A mechanism of degradation and breakdown in highk/ metal gate transistors was investigated. Based on the electrical test, physical analysis, and modeling results, we propose that the breakdown path formation/evolution in the interfacial SiO2 layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. The model allows reproducing SILC temperature dependency and its exponential increase from the fresh through soft and progressive breakdown phases.

G. Bersuker, D. Heh, J. Huang, C.S. Park, A. Padovani, L. Larcher, P. Kirsch, R. Jammy (2010) - Gate Leakage Current Reduction in Two-Step Processed High-k Dielectrics for Low Power Applications - International Conference on Solid State Devices and Materials (SSDM) - unknown unknown (JPN)) - pp. da 1034 a 1035 ISBN: 978XXXXXXXXX2 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

Reduction of the gate leakage current in nMOS high-k devices is demonstrated by an engineered two-step deposited Hf-based high-k dielectric film. The electrical characteristics and reliability of the devices fabricated using the proposed two-step and conventional one-step high-k gate stacks are shown to be comparable. The lower leakage current is attributed to the misalignment of the grain boundaries in the multi-layer high-k dielectrics.

G. Molas, L. Masoero, P. Blaise, A. Padovani, J. P. Colonna, E. Vianello, M. Bocquet, E. Nowak, M. Gasulla, O. Cueto, H. Grampeix, F. Martin, R. Kies, P. Brianceau, M. Gély, A. M. Papon, D. Lafond, J. P. Barnes, C. Licitra, G. Ghibaudo, L. Larcher, S. Deleonibus, B. De Salvo (2010) - Investigation of the impact of H-related defects in Al2O3 blocking layer of charge-trap memories by atomistic simulations and device physical modeling - Proc. IEDM - IEEE Piscataway (NJ, USA) (USA)) - pp. da 22.5 a 22.5 ISBN: 9781442474185 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this work, we use atomistic simulation, consolidated by a detailed Al2O3 physico-chemical material analysis, to investigate the origin of traps in Al2O3 (in particular, Al- or O-vacancies and H-interstitials). It is shown that the leakage currents through Al2O3 layers, with different post-deposition anneals, are strictly correlated to the H content. Then, for the first time at our knowledge, the hydrogen-based trap features estimated by quantum simulations are introduced in a TANOS device simulator. A very good agreement is obtained between model and device experimental data, allowing for a clear understanding of the role of alumina H content on the retention characteristics of charge-trap memories.

H. Park, G. Bersuker, D. Gilmer, K. Y. Lim, M. Jo, H. Hwang, A. Padovani, L. Larcher, P. Pavan, W. Taylor, P. D. Kirsch (2010) - Charge loss in TANOS devices caused by Vt sensing measurements during retention - Proc. of IEEE Intenrational Memory Workshop - IEEE Piscataway (NY, USA) (USA)) - pp. da 1 a 2 ISBN: 978-1-4244-6719-8 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In TANOS stuctures in retention, the major decrease in the programmed threshold voltage is found to be caused by the Vt sensing (IdVg measurements) rather than by intrinsic charge loss (when no bias is applied). This Vt decrease can be understood within the process of the temperature-activated charge transport through the Al2O3 blocking oxide. The charge loss can be minimized when Vt sensing time is decreased down to micro seconds. Blocking oxides engineered by adding a thin SiO2 layer at the SiN/AlO interface demonstrate significant suppression of the charge loss.

L. Larcher, A. Padovani (2010) - Fundamental reliability issues of advanced charge-trapping Flash memory devices - Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on - IEEE Piscataway (NJ, USA) (USA)) - pp. da 1009 a 1012 ISBN: 9781424481552 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

The basic reliability issues of Charge Trapping (CT) Flash memory devices will be discussed from a physical perspective, highlighting the reliability implications of process and technology innovations introduced to sustain the uninterrupted device scaling down. We will focus on the reliability issues related to the charge localization inside the trapping layer and the high-? band-gap engineered stacks introduced to implement both tunnel and blocking dielectrics. We will describe the physical mechanisms responsible of reliability degradation (data retention, array disturbs, endurance), discussing briefly the issues related to ultra-scaled and vertically stacked 3D Flash memory devices.

L. Morassi, A. Padovani, G. Verzellesi, D. Veksler, I. Ok, G.Bersuker (2010) - Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics - 19th European Workshop on Heterostructure Technology - unknown unknown (GRC)) - pp. da 1 a 2 ISBN: 978XXXXXXXXX2 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this paper, we use 2D numerical device simulations [Sentaurus Device, Synopsys Inc.] to investigate the impact of interface traps on the electrical characteristics of MOSFETs and MOSHEMTs with InGaAs channel and high-k gate dielectrics. More specifically, the following two technologies are taken into consideration: A) self-aligned inversion-type InGaAs/ZrO2 MOSFETs; B) implant-free InGaAs/Al2O3 MOSHEMTs.

L. Morassi, G. Verzellesi, A. Padovani, L. Larcher, P. Pavan, D. Veksler, Injo Ok, G. Bersuker (2010) - Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs - Proceedings of IRPS 2010 - IEEE Piscataway, NJ (USA)) - pp. da 532 a 535 ISBN: 978-1-4244-5431-0 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

Interface-trap effects are analyzed in inversion-type, self-aligned In0.53Ga0.47As and In0.53Ga0.47As/In0.2Ga0.8As MOSFETs with ALD ZrO2 gate dielectric. Interface-trap densities in the order of 1e13 cm-2 eV-1 are required to explain the measured subthreshold slopes. For these Dit values, donor-like interface traps are compatible with threshold-voltage values in the 0-0.15 V range as those observed in these devices. Moreover, the presence of donor-like interface traps can explain the negative threshold-voltage shift induced by the inclusion of the In0.2Ga0.8As cap layer, as the result of the influence of interface traps located at the In0.2Ga0.8As/ZrO2 interface on the inversion channel forming at the In0.53Ga0.47As/In0.2Ga0.8As interface.

L. Vandelli, A. Padovani, L. Larcher, G. Bersuker, R.G. Southwick III, W.B. Knowlton (2010) - Modeling Temperature Dependency (6 - 400K) of the Leakage Current Through the SiO2/High-K Stacks - ESSDERC, Tech. Proc. of - IEEE Piscataway (NJ, USA) (USA)) - pp. da 388 a 391 ISBN: 9781424466580 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

We investigate the mechanism of the gate leakage current in the Si/SiO2/HfO2/TiN stacks in a wide temperature range (6 – 400 K) by simulating the electron transport using a multi-phonon trap assisted tunneling model. Good agreement between simulations and measurements allows indentifying the dominant physical processes controlling the temperature dependency of the gate current. In depletion/weak inversion, the current is limited by the supply of carrier. In strong inversion, the electron-phonon interaction is found to be the dominant factor determining the current voltage and temperature dependencies. These simulations allowed to extract important defect parameters, e.g. the trap relaxation energy and phonon effective energy, which defines the defect atomic structure.

Luca Larcher, Andrea Padovani, Vincenzo della Marca, Paolo Pavan, Alessandro Bertacchini (2010) - Investigation of Trapping/detrapping Mechanisms in Al2O3 Electron/hole Traps and Their Influence on TANOS Memory Operations - Proceedings 2010 VLSI-TSA - ITRI Hsinchu (TWN)) - pp. da 52 a 53 ISBN: 9781424450640 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

The purpose of this work is to investigate the physics of electron/hole trapping/detrapping mechanisms in Al2O3. Combining I-V and C-V measurements with a physical model we derive the energy levels of electron/hole traps and the location of electron/hole charge. The influence of electron/hole alumina traps on TANOS operations and reliability is investigated.

Luca Vandelli, Andrea Padovani, Luca Larcher, Antonio Arreghini, Geert Van den bosch, Malgorzata Jurczak , Jan Van Houdt, Vincenzo Della Marca, Paolo Pavan (2010) - Role of Holes and Electrons During Erase of TANOS Memories: Evidences for Dipole Formation and its Impact on Reliability - Proceedings IRPS 2010 - IEEE Piscataway, N.J. (USA)) - pp. da 731 a 737 ISBN: 9781424454310 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

The systematic investigation of the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations is reported for the first time. We determined a dominance of electrons back-tunneling in the first part of the transient, and dominance of holes in the second part. Good agreement is reached between experimental and simulated data. In addition we demonstrate for the first time the formation of a vertical charge dipole in TANOS devices, whose polarity depends on the P/E operation sequence. This dipole severely affects the program and erase performances and the retention of mild programmed and erased states, which is a concern especially for multilevel applications.

S. Cimino, A. Padovani, L. Larcher, V.V. Afanas’ev, H. J. Hwang, Y. G. Lee, M. Jurczac, D. Wouters, B.H. Lee, H. Hwang, L. Pantisano (2010) - Leakage Current in TiN/HfO2/TiN MIM Capacitors and Degradation due to Electrical Stress - MA2010-02 - ECS - The Electrochemical Society Pennington (USA)) - n. volume E5 - High - pp. da 1532 a 1532 ISBN: 978XXXXXXXXX2 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

Metal Insulator Metal (MIM) capacitors are widely used in the electronic industry for DRAM as well as for analog applications. Defects in dielectric structures are very important as they control not only gate leakage and power consumption but, also, device noise and lifetime. Physical and electrical characteristics of TiN/HfO2/TiN capacitors have been investigated aiming at the study of defects and defect energy position in HfO2 on TiN.

V. Della Marca, F. Carboni, L. Larcher, A. Padovani, P. Pavan (2010) - SET switching effects on PCM endurance - ESSDERC, Tech. Proc. of - IEEE Piscataway (NJ, USA) (USA)) - pp. da 321 a 324 ISBN: 9781424466580 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this paper we report results on PCM endurance failure characterization. We show that endurance failure is related to SET pulse features and we analyze and model SET operation to obtain a better understanding and improve endurance performance. Results give interesting insights on the crystallization process of GST material. SET obeys to a constant energy law. Fast SET pulses require high power; slow SET pulses can be implemented in low power applications. Results may be used for optimized SET/RESET operation to achieve better endurance.

P.Pavan, L. Larcher, A. Padovani, A. Bertacchini (2009) - MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems [Attività collegate alla Ricerca - Partecipazione a progetti di ricerca]
Abstract

The objective of the MODERN project is to develop new paradigms in integrated circuit design which will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. Specifically, the main goals of the project are: 1. Advanced, yet accurate, models of process variations for nanometer devices, circuits and complex architectures. 2. Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. Reliability, noise, EMC/EMI. Timing, power and yield. 3. Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels. 4. Validation of the modeling and design methods and tools on a variety of silicon demonstrators.

A. Padovani, L. Larcher, D. Heh, G. Bersuker (2009) - Modeling TANOS Memory Program Transients to Investigate Charge Trapping Dynamics - IEEE ELECTRON DEVICE LETTERS - n. volume 30(8) - pp. da 882 a 884 ISSN: 0741-3106 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

A novel physics-based drift-diffusion model of TANOS program transients is employed to investigate electron trapping and detrapping dynamics in the nitride trapping layer. Trapping process is found to be independent from the energy of injected electrons, while detrapping is dominated by trap-to-band tunneling. Modeling of the trapped charge evolution during program transients allows to extract physical characteristics of the traps and provides useful information for the optimization of TANOS memories.

L. Larcher, P. Pavan, A. Padovani, G. Ghidini (2009) - A technique to extract high-k IPD stack layer thicknesses from C-V measurements - IEEE ELECTRON DEVICE LETTERS - n. volume 30(6) - pp. da 653 a 655 ISSN: 0741-3106 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

We propose in this letter a simple technique based on C-V measurements which allows to estimate the thicknesses of SiOX and high-k layers of IPD stacks. We apply this technique to IPD Al2O3-based stacks for floating gate memory applications, finding a good agreement with TEM measurements. In addition, simulation results are provided to demonstrate the correctness of the basic assumption of this technique.

G. Bersuker, D. Veksler, C. D. Young, H. Park, L. Morassi, A. Padovani, L. Larcher, W. Taylor, P. D. Kirsch, and R. Jammy (2009) - Connecting electrical and structural dielectric characteristics - Advanced Workshop on 'Frontiers in Electronics - unknown unknown (USA)) - pp. da 1 a 2 ISBN: 978XXXXXXXXX2 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

unknown

L. Morassi, L. Larcher, L. Pantisano, A. Padovani, R. Degreave, M. B. Zahid, and B. J. O'Sullivan (2009) - Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing - 41th International Conference on Solid State Devices and Materials - unknown unknown (JPN)) - pp. da 1 a 2 ISBN: 978XXXXXXXXX2 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

This paper presents an original approach for material studies for memory devices where the degree of intermixing between the high-k and interfacial SiO2 is explicitly quantified experimentally. Using calibrated leakage simulation the importance of intermixing is verified independently together with the conduction mechanism. The implication for NVM reliability are profound and will be discussed toward retention mechanisms and used to optimize retention margins for NVM memories.

S. Verma, G. Bersuker, D.C. Gilmer, A. Padovani, P. Hokyung, A. Nainani, D. Heh, J. Huang, J. Jiang, K. Parat, P.D. Kirsch, L. Larcher, Hsing-Huang Tseng, K.C. Saraswat, R. Jammy (2009) - A Novel Fluorine Incorporated Band Engineered (BE) Tunnel (SiO2/ HfSiO/ SiO2) TANOS with Excellent Program/Erase & Endurance to 10^5 Cycles - Memory Workshop, 2009. IMW '09. IEEE International - IEEE Piscataway (USA)) - pp. da 1 a 2 ISBN: 978-1-4244-3762-7 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

We demonstrate for the first time a fluorine incorporated band- engineered (BE) tunnel oxide (SiO2/HfSiO/SiO2) TANOS with excellent program / erase (P/E) characteristics and endurance to 105 cycles. Incorporating fluorine in the tunnel dielectric improves Si/SiO2 interface resulting in excellent endurance of nearly constant over 3 V P/E window for at least 105 cycles. Fluorine also reduces interface state generation during retention by ~20%. Furthermore, Fluorine passivates bulk traps leading to as much as ~10times higher charge to breakdown (Qbd) and ~10-50times lower interface state density (Dit). Fluorine passivation for BE-TANOS is significant because it improves reliability assisting implementation of TANOS flash NVM beyond the 20 nm node.

S. Verma, G. Bersuker, D. C. Gilmer, A. Padovani, H. Park, A. Nainani, J. Huang, K. Parat, P. D. Kirsch, L. Larcher, H.-H. Tseng, K. C. Saraswat R. Jammy (2009) - Understanding endurance degradation in Flash memory through transconductance measurement - 6th International Symposium on Advanced Gate Stack Technology - unknown unknown (USA)) - pp. da 1 a 2 ISBN: 978XXXXXXXXX2 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

Endurance degradation is a limitation for implementing futurescaled flash memory devices. This degradation is mainly attributableto Si/SiO2 interface traps generated during program/erase (P/E) stress rather than fixed charges in the bulk oxide. In this work, we use Gm (transconductance) to monitor the interface degradation. Wereport that interface defect generation is highest during erase operation. In addition to the interface, hole & electron tunnelingprobability seem crucial to degradation during erase. Fluorine incorporation in tunnel stack is found to reduce Gm degradationsuggesting improved interface.

A. Padovani, L. Larcher, P. Pavan (2008) - Hole Distributions in Erased NROM Devices: profiling method and effects on reliability - IEEE TRANSACTIONS ON ELECTRON DEVICES - n. volume 55 - pp. da 343 a 348 ISSN: 0018-9383 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

The NROM-cell concept has been introduced as a promising technology to replace Flash nonvolatile memory devices also in embedded products, owing to its intrinsic 2-b/cell operation and better endurance. However, the presence of physically sepa- rated electron and hole distributions generated by program and erase operations is reported to be one of the main causes of the device’s retention degradation. Therefore, a deep knowledge of the features and evolution of the nitride-storage charge is crucial for reliability, cell optimization, future scalability, and multilevel oper- ation. In this scenario, the purpose of this paper is twofold, which is as follows: 1) to introduce a combined simulative experimental method allowing pro?ling hole distribution in devices erased with different bias conditions and 2) to monitor through this technique the evolution of the nitride charge with cycling, correlating it to the degradation of memory reliability after cycling.

L. LARCHER; A. PADOVANI; P. PAVAN; P. FANTINI; A. CALDERONI; A. MAURI; A. BENVENUTI (2008) - Modeling NAND Flash Memories for IC Design - IEEE / Institute of Electrical and Electronics Engineers Incorporated:445 Hoes Lane:Piscataway, NJ 08854:(800)701-4333, (732)981-0060, EMAIL: subscription-service@ieee.org, INTERNET: http://www.ieee.org, Fax: (732)981-9667) - IEEE ELECTRON DEVICE LETTERS - n. volume 29(10) - pp. da 1152 a 1154 ISSN: 0741-3106 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

In this letter, we present a compact model of NAND Flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simula- tion of NAND Flash memories with a limited computational effort, taking into account capacitive coupling effects which will become extremely important in future technology generations. This model is a very valuable tool for IC designers to optimize NVM circuits, particularly in multilevel applications.

A. Padovani, L. Larcher, S. Verma, P. Pavan, P. Majhi, P. Kapur, K. Parat, G. Bersuker, K. Saraswat (2008) - Feasibility of SIO2/Al2O3 tunnel dielectric for future Flash memories generations - 9th Ultimate Integration on Silicon Conference (IEEE ULIS) - IEEE Piscataway (USA)) - pp. da 111 a 114 ISBN: 9781424417292 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this paper, we investigate the feasibility of SiO2/Al2O3 stack tunnel dielectric for future Flash memory generations using statistical leakage current simulations. We show that the statistical Monte Carlo (MC) simulator we employed reproduces accurately leakage currents measured on SiO2/Al2O3 dielectric capacitors. Exploiting its statistical capabilities, we calculate leakage current distributions in Flash memory retention conditions. We show that the high defectiveness of AI2O3 stacks strongly reduces the potential improvement of Flash retention due to the introduction of AI2O3 tunnel dielectric.

A. Padovani, L. Larcher, S. Verma, P. Pavan, P. Majhi, P. Kapur, K. Parat, G. Bersuker, K. Saraswat (2008) - Statistical modeling of leakage currents through SiO2/high-k dielectric stacks for non-volatile memory applications - Reliability Physics Symposium, 2008. IRPS 2008. IEEE International - IEEE Piscataway (USA)) - pp. da 616 a 620 ISBN: 978-1-4244-2049-0 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-kappa dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-kappapsilas traps on leakage current distribution for flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-kappa tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-kappa tunnel stacks and to improve technology reliability issues related to flash memory applications.

G. Bersuker, D. Heh, C. Young, H. Park, P. Khanal, L. Larcher, A. Padovani, P. Lenahan, J. Ryan, B.H. Lee, H. Tseng, R. Jammy (2008) - Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric - Electron Devices Meeting, 2008. IEDM 2008. IEEE International - IEEE Piscataway (USA)) - pp. da 1 a 4 ISBN: 978-1-4244-2377-4 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

We apply a systematic approach to identify a high-k/metal gate stack degradation mechanism. Our results demonstrate that the SiO2 interfacial layer controls the overall degradation and breakdown of the high-k gate stacks stressed in inversion. Defects contributing to the gate stack degradation are associated with the high-k/metal-induced oxygen vacancies in the interfacial layer.

G. Puzzilli, F. Irrera, A. Padovani, P. Pavan, L. Larcher, A. Arya, V. Della Marca, A. Pirovano (2008) - On the RESET-SET transition in Phase Change Memories - Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European - IEEE Piscataway (USA)) - pp. da 158 a 161 ISBN: 978-1-4244-2363-7 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

We characterize SET operation in Phase Change Memories. A measurement procedure aiming to investigate resistance transition from amorphous to crystalline states is shown. Results give interesting insights on the crystallization process of GST material and a simple model is introduced. Crystallization process obeys to a constant energy law. Fast SET pulses require high power; slow SET pulses can be implemented in low power applications. Results may be used for an optimized design of memory cell operating conditions.

A. Padovani, L. Larcher, A. Chimenton, P. Pavan, P. Olivo (2007) - Dielectric Reliability for Future Logic and Non-Volatile Memory Applications: a Statistical Simulation Analysis Approach - Electrochemical Society:65 South Main Street, Building D:Pennington, NJ 08534:(609)737-1902, EMAIL: ecs@electrochem.org, orders@electrochem.org, INTERNET: http://www.electrochem.org, Fax: (609)737-2743) - JOURNAL OF THE ELECTROCHEMICAL SOCIETY - n. volume 8 - pp. da 237 a 242 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

In this paper, we present a physically-based Monte-Carlo (MC) model reproducing the leakage current flowing across typical dielectric layers (SiO2, high-k) used in ULSI technologies. Simulations will be shown to predict accurately currents measured on MOSFETs, large area MOS capacitor, and tunnel oxides of Flash memories after electrical and radiation stresses. Statistical aspects related to leakage current and threshold voltage are reproduced correctly, allowing worst case corner prediction, necessary to assess dielectric damaging effects on logic circuits and non-volatile memory operation.

A. PADOVANI; L. LARCHER; P. PAVAN; L. AVITAL; I. BLOOM; B. EITAN (2007) - ID-VGS Based Tools to Profile Charge Distributions on NROMTM Memory Devices - IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY - n. volume 7 - pp. da 97 a 104 [Pubblicazione in Rivista - Articolo pubblicato in Rivista]
Abstract

The NROM cell concept has been introduced as a promising technology to replace Flash non-volatile memory devices also in embedded products, thanks to its intrinsic two-bits/cell operation and better endurance. However, the presence of physically separated electron and hole distributions generated by program and erase operations is reported to be one of the main causes of device’s retention degradation. Therefore, a deep knowledge of the features and evolution of the nitride storage charge is crucial for reliability, cell optimization, future scalability and multi-level operation. In this scenario, the purpose of this paper is twofold: 1) to introduce a combined simulative-experimental method allowing profiling hole distribution in devices erased with different bias conditions; 2) to monitor through this technique the evolution of the nitride charge with cycling, correlating it to the degradation of memory reliability after cycling.

A. Padovani, A. Chimenton, P. Olivo, P. Fantini, L. Vendrame, and S. Mennillo (2007) - Statistical Methodologies for Integrated Circuits Design - 3nd Conference on Ph.D. Research in Microelectronics and Electronics - IEEE Piscataway (USA)) - pp. da 277 a 280 ISBN: 9781424410002 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

The continuous scaling of physical dimensions has strongly increased circuit performance variability and the traditional corner-case methodology is becoming unreliable. As a consequence, there is an urgent need for new and more accurate statistical models. In this scenario, the purpose of this paper is twofold: 1) to give the reader the basic concepts of statistical modeling, and 2) to discuss a viable statistical approach that could be adopted into a traditional IC design flow for the next technology generations.

A. Padovani, L. Larcher, A. Chimenton, P. Pavan (2007) - Monte-Carlo Simulations of Flash Memory Array Retention (unknown - IEEE International Symposium on VLSI Technology, Systems and Applications (IEEE VLSI-TSA) - IEEE Piscataway (USA)) - n. volume 1 - pp. da 156 a 157 ISBN: 1424405858 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

One of the major scalability limitations of flash memories is anomalous SILC, which strongly endangers device reliability and data retention. Therefore, an accurate evaluation of SILC statistics on large arrays is crucial for reliability predictions and new Flash technology development. In the last years, oxide leakage currents were deeply investigated and modeled, neglecting SILC statistics and effects on large Flash arrays. More recently, analytical models relating Flash statistical threshold voltage (VT) distributions to defect statistics and leakage current were proposed. However, these models rely on several simplifying assumptions such as the equivalent cell concept and an uniform defect population. Still, these models do not account for the initial VT distribution and neglect the role played by trap energy and effective field. In this scenario, the purpose of this paper is to present a Monte-Carlo (MC) simulator reproducing flash VT distribution, which overcomes the above model limitations. We will show that this model can be used to 1) investigate effects of defect features and technology parameters on VT distribution, and 2) analyze the impact of temperature and voltage accelerated stresses on final VT distribution.

A. Padovani, L. Larcher, and P. Pavan (2007) - Hole Distributions in NROM Devices: Profiling Technique and Correlation to Memory Retention (unknown - 45th IEEE International Reliability Physics Symposium (IEEE IRPS) - IEEE Piscataway (USA)) - n. volume 1 - pp. da 654 a 655 ISBN: 1424409195 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this work, we presented a new technique to profile hole distribution in NROM devices. The evolution of the nitride charge in cycled cells was monitored. The key role played by holes in NROM retention degradation was identified. Electron injection far from the junction and VT drift in erased NROM cells are successfully explained.

L. LARCHER, A. PADOVANI, I. RIMMAUDO, P. PAVAN, A. CALDERONI, G. MOLTENI, F. GATTEL, P. FANTINI (2007) - Modeling NAND Flash memories for circuit simulations - International Conference on Simulation of Semiconductor Processes and Devices, IEEE SISPAD 2007 - Springer-Verlag Wien New York (USA)) - pp. da 293 a 296 ISBN: 978-3-211-72860-4 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

In this paper, we will present the basic structure and the parameter extraction procedure for a compact model of a NAND Flash memory string working in Spice-like circuit simulators. To the author knowledge, this is the first Spice-like model of a NAND Flash memory string. This model is modular and simple to be implemented. It will allow accurately reproducing both DC and transient behavior of NAND Flash memories without increasing computational effort, thus becoming an indispensable tool for designers to optimize circuits especially in multi-level applications.

A. PADOVANI, L. LARCHER, P. PAVAN (2006) - Profiling charge distribution in NROM devices - Research in Microelectronics and Electronics 2006, Ph. D. - IEEE Piscataway (USA)) - pp. da 69 a 72 ISBN: 1-4244-0157-7 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

NROM memory cells are proposed as one of the most promising non-volatile memories. Issues on scaling and endurance have risen due to the presence of both electrons and holes, for the control of their relative position and spread in the charge trapping material. Therefore, a deeper analysis of the injected-charge distribution region is very important for program/erase bias optimization, reliability prediction and future scaling. In this paper, we introduce and discuss two tools, based on subthreshold slope and temperature effects, able to correctly estimate program charge distribution features from simple ID - VGS measurements

L. AVITAL, A. PADOVANI, L. LARCHER, I. BLOOM, R. ARIE, P. PAVAN, B. EITAN (2006) - Temperature Monitor: a New Tool to Profile Charge Distribution in NROMTM Memory Devices - Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International - IEEE Piscataway (USA)) - pp. da 534 a 540 ISBN: 0-7803-9498-4 [Atto di Convegno (in Volume) - Relazione in Volume di Atti di Convegno]
Abstract

NROM memory cells are proposed as one of the most promising non-volatile memories. Issues on scaling and endurance have risen due to the presence of both electrons and holes for the control of their relative position and spread in the charge trapping material. In this paper, we present a new characterization tool able to sense charge distribution features in different program/erase conditions that can be efficiently used for program/erase bias optimization and reliability predictions. This new tool exploits temperature effects on ID-VGS current measurements