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RUBEN ASANOVSKI

Dottorando
Dipartimento di Ingegneria "Enzo Ferrari"

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Pubblicazioni

2024 - Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis [Articolo su rivista]
Asanovski, R.; Arimura, H.; de Marneffe, J. -F.; Palestri, P.; Horiguchi, N.; Kaczer, B.; Selmi, L.; Franco, J.
abstract

2024 - Characterization of DC performance and low-frequency noise of an array of nMOS Forksheets from 300 K to 4 K [Articolo su rivista]
Asanovski, R.; Grill, A.; Franco, J.; Palestri, P.; Mertens, H.; Ritzenthaler, R.; Horiguchi, N.; Kaczer, B.; Selmi, L.
abstract

2023 - Assessment of Advanced Nanoscale Bulk FinFET's Self-Heating accounting for degraded thermal conductivity at the nanoscale [Poster]
Tondelli, Lisa; Asanovski, Ruben; Selmi, Luca
abstract

We report self-consistent electrothermal simulations of large RF FinFET structures accounting for the multiscale effects of large BEOL metallizations and nanoscale device dimensions. A 6 fins x 4 fingers (24 channels) elementary cells is taken as a template reference device inspired by large RF transistors in 14-25 nm FinFET technology. Thermal resistances are extracted by means of the so-called AC small signal technique. The results highlight the sensitivity of the Rth to numerous geometrical and technological parameters, and the detrimental impact that reduced fin width and interfaces have on the thermal conductivity. The average temperature increase computed from the simulated thermal resistance provides useful guidelines for the design of RF FinFETs with lower maximum temperature, improved self-heating effects and reliability.

2023 - Investigating the correlation between interface and dielectric trap densities in aged p-MOSFETs using current-voltage, charge pumping, and 1/f noise characterization techniques [Articolo su rivista]
Asanovski, Ruben; Franco, Jacopo; Palestri, Pierpaolo; Kaczer, Ben; Selmi, Luca
abstract

2023 - Understanding the Excess 1/f Noise in MOSFETs at Cryogenic Temperatures [Articolo su rivista]
Asanovski, R; Grill, A; Franco, J; Palestri, P; Beckers, A; Kaczer, B; Selmi, L
abstract

Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature ( $ extit{T}$ ), referred to as "excess 1/f noise ", observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures.

2022 - Importance of Charge Trapping/Detrapping Involving the Gate Electrode on the Noise Currents of Scaled MOSFETs [Articolo su rivista]
Asanovski, R.; Palestri, P.; Selmi, L.
abstract

Carrier trapping/detrapping from/to the gate into dielectric traps is often neglected when modeling noise in MOSFETs and, to the best of our knowledge, no systematic study of its impacts on scaled devices is available. In this article, we show that this trapping mechanism cannot be neglected in nowadays aggressively scaled gate dielectric thicknesses without causing errors up to several orders of magnitude in the estimation of the drain current noise. The noise generation mechanism is modeled analytically and then analyzed through the use of 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures and channel/gate-stack materials. The results provide new insights for technology and device designers, highlight the relevance of the choice of the gate metal work function (WF) and the role of valence band electron trapping at high gate voltages.

2022 - New insights on the excess 1/f noise at cryogenic temperatures in 28 nm CMOS and Ge MOSFETs for quantum computing applications [Relazione in Atti di Convegno]
Asanovski, R.; Grill, A.; Franco, J.; Palestri, P.; Beckers, A.; Kaczer, B.; Selmi, L.
abstract

2022 - On the accuracy of the formula used to extract trap density in MOSFETs from 1/f noise [Relazione in Atti di Convegno]
Asanovski, R.; Palestri, P.; Selmi, L.
abstract

Noise spectroscopy is a powerful non-destructive technique to characterize the quality of gate dielectrics in MOSFETs. Trap densities are routinely extracted by fitting the 1/f part of the drain current noise spectrum with a widely known analytical expression containing several approximations within. This paper compares this 1/f noise analytical expression with microscopic simulations, evaluates its accuracy under different scenarios, and highlights when the main assumptions fall short. It is found that the expression agrees well with non-radiative multi-phonon (NMP) models at room temperature for devices featuring a thick dielectric. However, the formula fails to correctly predict the noise of nowadays aggressively scaled devices, because it neglects trapping/de-trapping with the gate electrode and the electrostatic charge scaling of the traps due to their distance from the channel.

2021 - A Comprehensive Gate and Drain Trapping/Detrapping Noise Model and Its Implications for Thin-Dielectric MOSFETs [Articolo su rivista]
Asanovski, R.; Palestri, P.; Caruso, E.; Selmi, L.
abstract

We derive a complete set of expressions for the MOSFET gate and drain power spectral densities due to elastic and inelastic trapping/detrapping of channel carriers into the gate dielectric. Our calculations explain trapping/detrapping noise (TDN) in various FET operating regions and highlight trap's position-dependent terms, often neglected in the literature, which are instead important for devices with thin gate dielectrics. Furthermore, we show that TDN has a contribution to the gate current noise, correlated with the drain current fluctuations and we highlight the role of the transfer function between channel charge fluctuations and drain current on the noise characteristics. The model expressions are carefully validated by comparison with 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures (bulk, fully depleted-silicon-on-insulator (FD-SOI), FinFET), channel, and gate materials. Besides shedding new light on TDN, the results could enable trap density extraction from experimental samples with improved accuracy and pave the way to complete and accurate compact models for TDN in MOSFETs.

2020 - 1/f noise model based on trap-assisted tunneling for ultra-thin oxides MOSFETs [Abstract in Atti di Convegno]
Caruso, Enrico; Palestri, Pierpaolo; Selmi, Luca; Asanovski, Ruben
abstract

We derive an analytical model for 1/f noise in MOSFETs, highlighting a term that is often neglected in literature but becomes important for ultra-thin oxides. Furthermore, we identify an interesting relationship between the thermal noise of the gate impedance and the gate noise due to trapping/detrapping between the free carriers in the channel and the oxide traps, as well as the 1/f noise cross-correlation between drain and gate, showing that a single voltage noise generator is not enough to describe completely the 1/f noise. TCAD simulations are used to verify the model predictive capabilities.