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ANDREA PADOVANI

Ricercatore t.d. art. 24 c. 3 lett. B
Dipartimento di Ingegneria "Enzo Ferrari"

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Pubblicazioni

2024 - Estimating the Number of Defects in a Single Breakdown Spot of a Gate Dielectric [Articolo su rivista]
Ranjan, A.; Padovani, A.; Dianat, B.; Raghavan, N.; Pey, K. L.; O’Shea, S. J.
abstract

2024 - The Role of Carrier Injection in the Breakdown Mechanism of Amorphous Al2O3 Layers [Articolo su rivista]
La Torraca, P.; Padovani, A.; Strand, J.; Shluger, A.; Larcher, L.
abstract

2023 - A HydroDynamic Model for Trap-Assisted Tunneling Conduction in Ovonic Devices [Articolo su rivista]
Buscemi, F; Piccinini, E; Vandelli, L; Nardi, F; Padovani, A; Kaczer, B; Garbin, D; Clima, S; Degraeve, R; Kar, Gs; Tavanti, F; Slassi, A; Calzolari, A; Larcher, L
abstract

Electrical conduction in ovonic threshold switching (OTS) devices is described by introducing a new physical model where the multiphonon trap-assisted tun-neling (TAT) is coupled to a hydrodynamic theory. Static and transient electrical responses from Ge(x)Se(1-x )experimental devices are reproduced, outlining the role played by the material properties like mobility gap and defects in tuning the OTS performances. A clear physical interpretation of the mechanisms ruling the different OTS conduction regimes (off, threshold, on) is presented. A nanoscopic picture of the processes featuring the carrier transport is also given. The impact of geometry, temperature, and material mod-ifications on device performance is discussed providing physical insight into the optimization of OTS devices.

2023 - A simple figure of merit to identify the first layer to degrade and fail in dual layer SiOx/HfO2 gate dielectric stacks [Articolo su rivista]
Padovani, Andrea; La Torraca, Paolo
abstract

Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k (HK) gate dielectric stack is crucial for the improvement of device reliability. We present a new Figure of Merit (FoM), the IL/HK Degradation Index, that depends on fundamental materials properties (the dielectric breakdown strength and the dielectric constant) and can be used to easily and quickly identify the first layer to degrade and fail in a bilayer SiO2/HK dielectric stack. Its dependence on IL and HK material parameters is investigated and its validity is demonstrated by means of accurate physics-based simulations of the degradation process. The proposed FoM can be easily used to understand the degradation dynamics of the gate dielectric stack, providing critical insights for device reliability improvement.

2023 - Adhesion Microscopy as a Nanoscale Probe for Oxidation and Charge Generation at Metal-Oxide Interfaces [Articolo su rivista]
Ranjan, A.; Padovani, A.; Dianat, B.; Raghavan, N.; Pey, K. L.; O'Shea, S. J.
abstract

2023 - Device‐to‐Materials Pathway for Electron Traps Detection in Amorphous GeSe‐Based Selectors [Articolo su rivista]
Slassi, Amine; Medondjio, Linda‐sheila; Padovani, Andrea; Tavanti, Francesco; He, Xu; Clima, Sergiu; Garbin, Daniele; Kaczer, Ben; Larcher, Luca; Ordejón, Pablo; Calzolari, Arrigo
abstract

The choice of the ideal material employed in selector devices is a tough task both from the theoretical and experimental side, especially due to the lack of a synergistic approach between techniques able to correlate specific material properties with device characteristics. Using a material-to-device multiscale technique, we propose a reliable protocol for an efficient characterization of the active traps in amorphous GeSe chalcogenide. The resulting trap maps trace back the specific features of materials responsible for the measured findings, and connect them to an atomistic description of the sample. Our metrological approach can be straightforwardly extended to other materials and devices, which is very beneficial for an efficient material-device co-design and the optimization of novel technologies.

2023 - Electrically active defects in Al2O3-InGaAs MOS stacks at cryogenic temperatures [Relazione in Atti di Convegno]
La Torraca, Paolo; Padovani, Andrea; Wernersson, Lars-Erik; Cherkaoui, Karim; Hurley, Paul; Larcher, Luca
abstract

2023 - High-k/InGaAs interface defects at cryogenic temperature [Articolo su rivista]
Cherkaoui, K.; La Torraca, P.; Lin, J.; Maraviglia, N.; Andersen, A.; Wernersson, L. E.; Padovani, A.; Larcher, L.; Hurley, P. K.
abstract

2023 - Insights into device and material origins and physical mechanisms behind cross temperature in 3D NAND [Relazione in Atti di Convegno]
Pesic, Milan; Beltrando, Bastien; Rollo, Tommaso; Zambelli, Cristian; Padovani, Andrea; Micheloni, Rino; Maji, Rita; Enman, Lisa; Saly, Mark; Bae, Yang Ho; Kim, Jung Bae; Yim, Dong Kil; Larcher, Luca
abstract

2023 - Modeling Degradation and Breakdown in SiO2 and High-k Gate Dielectrics [Relazione in Atti di Convegno]
Padovani, Andrea; Torraca, Paolo La; Larcher, Luca; Strand, Jack; Shluger, Alexander
abstract

We present a multiscale device simulation framework for modeling degradation and breakdown (BD) of gate dielectric stacks. It relies on an accurate, material-dependent description of the most relevant defect-related phenomena in dielectrics (charge trapping and transport, atomic species generation), and self-consistently models all degradation phases within the same physics-based description: stress-induced leakage current (SILC), soft (SBD), progressive (PBD) and hard breakdown (HBD). This methodology is applied to understand several key aspects related to the reliability of SiO2 and high-k (HK) gate dielectrics: i) characterization and role of defects responsible for the charge transport in fresh and stressed devices (SILC); ii) the differences observed in the SILC behavior of nMOS and pMOS transistors; iii) the degradation of bilayer SiOx/HfO2 stacks; and iv) the voltage dependence of the time-dependent dielectric breakdown (TDDB) distribution.

2023 - Molecular Bridges Link Monolayers of Hexagonal Boron Nitride during Dielectric Breakdown [Articolo su rivista]
Ranjan, A; O'Shea, Sj; Padovani, A; Su, T; La Torraca, P; Ang, Ys; Munde, Ms; Zhang, Ch; Zhang, Xx; Bosman, M; Raghavan, N; Pey, Kl
abstract

We use conduction atomic force microscopy (CAFM) to examine the soft breakdown of monocrystalline hexagonal boron nitride (h-BN) and relate the observations to the defect generation and dielectric degradation in the h-BN by charge transport simulations and density functional theory (DFT) calculations. A modified CAFM approach is adopted, whereby 500 x 500 nm2 to 3 x 3 mu m2 sized metal/h-BN/ metal capacitors are fabricated on 7 to 19 nm-thick h-BN crystal flakes and the CAFM tip is placed on top of the capacitor as an electrical probe. Current-voltage (I-V) sweeps and time-dependent dielectric breakdown measurements indicate that defects are generated gradually over time, leading to a progressive increase in current prior to dielectric breakdown. Typical leakage currents are around 0.3 A/cm2 at a 10 MV/cm applied field. DFT calculations indicate that many types of defects could be generated and contribute to the leakage current. However, three defects created from adjacent boron and nitrogen monovacancies exhibit the lowest formation energy. These three defects form molecular bridges between two adjacent h-BN layers, which in turn "electrically shorts" the two layers at the defect location. Electrical shorting between layers is manifested in charge transport simulations, which show that the I-V data can only be correctly modeled by incorporating a decrease in effective electrical thickness of the h-BN as well as the usual increase in trap density, which, alone, cannot explain the experimental data. An alternative breakdown mechanism, namely, the physical removal of h-BN layers under soft breakdown, appears unlikely given the h-BN is mechanically confined by the electrodes and no change in AFM topography is observed after breakdown. High-resolution transmission electron microscope micrographs of the breakdown location show a highly localized (<1 nm) breakdown path extending between the two electrodes, with the h-BN layers fractured and disrupted, but not removed.

2023 - The Major Effect of Trapped Charge on Dielectric Breakdown Dynamics and Lifetime Estimation [Relazione in Atti di Convegno]
Vecchi, Sara; Padovani, Andrea; Pavan, Paolo; Puglisi, Francesco Maria
abstract

2023 - Towards a Universal Model of Dielectric Breakdown [Relazione in Atti di Convegno]
Padovani, Andrea; Torraca, Paolo La; Strand, Jack; Shluger, Alexander; Milo, Valerio; Larcher, Luca
abstract

2022 - Atomic Defects Profiling and Reliability of Amorphous Al2O3 Metal–Insulator–Metal Stacks [Articolo su rivista]
Torraca, P. La; Caruso, F.; Padovani, A.; Tallarida, G.; Spiga, S.; Larcher, L.
abstract

We present a comprehensive characterization of amorphous alumina (a-Al2O3) high- k dielectric in metal-insulator-metal (MIM) stacks, self-consistently extracting the space-energy distribution of a-Al2O3 atomic defects and the related bond-breaking process parameters. Active defects are profiled via simultaneous simulation of current-voltage ( I- V), capacitance-voltage ( CV), conductance-voltage (GV) (i.e., defect spectroscopy), and low-field I- V hysteresis analysis. The defect energies extracted ( ETH = 1.55 and 3.55 eV) are consistent with oxygen vacancies and aluminum interstitials. The voltage-dependent dielectric breakdown (VDDB) statistics of a-Al2O(3) is investigated using ramped voltage stress (RVS). The VDDB statistics show a complex and polaritydependent breakdown statistics, correlating with defect distributions, which allows estimating the a-Al2O3 bondbreaking parameters with the support of multiscale atomistic simulations of the breakdown process.

2022 - BELLO: A post-processing tool for the local-order analysis of disordered systems [Articolo su rivista]
Dianat, B.; Tavanti, F.; Padovani, A.; Larcher, L.; Calzolari, A.
abstract

The characterization of the atomic structure of disordered systems, such as amorphous, glasses and (bio)molecule in solution, is a fundamental step for most theoretical investigations. The properties of short- and medium-range local order structures are responsible for the electronic, optical and transport properties of these systems. Here, we present the BELLO open source code, a post-processing script-tool created for the automatic analysis and extraction of structural characteristics of disordered and amorphous systems. BELLO is agnostic to the code that generated single configurations or trajectories, it provides an intuitive access through a graphical user interface (GUI), and it requires minimal computational resources. Its capabilities include the calculation of the order parameter q, the folded structure identification, and statistical analysis tools such as atomic coordination number and pair/angle-distribution functions. The working principles of the code are described and tested on ab initio molecular dynamics trajectories of amorphous chalcogenides.

2022 - Dielectric breakdown in HfO2 dielectrics: Using multiscale modeling to identify the critical physical processes involved in oxide degradation [Articolo su rivista]
Strand, Jack; La Torraca, Paolo; Padovani, Andrea; Larcher, Luca; Shluger, Alexander L.
abstract

2022 - Electron-assisted switching in FeFETs: Memory window dynamics - retention - trapping mechanisms and correlation [Relazione in Atti di Convegno]
Pesic, M.; Beltrando, B.; Padovani, A.; Miyashita, T.; Kim, N. -S.; Larcher, L.
abstract

We investigate the impact of charge-trapping on ferroelectric (FE) switching and its influence on memory window (MW) and retention of FeFET. Fabricated FinFETs with ferroelectric gate stack were used to study defects properties (within HZO), trapping/FE-switching interplay, and dynamics. Starting from the electronic-assisted nucleation of FE domains, we investigated the interface charging and degradation, as well as their impact on the polarization compensation, MW and stabilization of the retention. Finally, a balance between those competing processes was analyzed and a retention model of FeFET (capturing behavior over device's lifetime) was developed.

2022 - Investigation of Coercive Field Shift During Cycling in HfZrOₓ Ferroelectric Capacitors [Articolo su rivista]
Cai, P.; Li, H.; Liu, Z.; Zhu, T.; Zeng, M.; Ji, Z.; Wu, Y.; Padovani, A.; Larcher, L.; Pesic, M.; Wang, R.; Huang, R.
abstract

To fully understand the mechanisms for shifting of coercive field ( $E_{c}$ ) during the bipolar stress cycling in doped HfO₂ ferroelectric (FE) material, we present a systematic study with both characterization and simulation on HfZrOₓ (HZO) capacitor. First, with the help of time-dependent dielectric breakdown (TDDB) results, defect redistribution is found to be localized during the bipolar stress cycling. Then, with the advanced simulation framework GinestraⓇ, influences of work function (WF) mismatch of the electrodes and defect distribution on the $E_{c}$ symmetry and breakdown property are discussed. It indicates that the shift of $E_{c}$ is mostly due to the redistribution of defects from FE phase to non-FE phase and grain boundaries. Furthermore, nucleation limited switching (NLS) model is adopted to investigate the switching dynamics during coercive field shift in more detail.

2022 - Pulse optimization and device engineering of 3D charge-trap flash for synaptic operation [Articolo su rivista]
Anik Kumar, Mondol; Padovani, Andrea; Larcher, Luca; Raiyan Chowdhury, S. M.; Zunaid Baten, Md
abstract

2022 - Reliability of Non-Volatile Memory Devices for Neuromorphic Applications: A Modeling Perspective (Invited) [Relazione in Atti di Convegno]
Padovani, A.; Pesic, M.; Nardi, F.; Milo, V.; Larcher, L.; Kumar, M. A.; Baten, M. Z.
abstract

The advent of Artificial Intelligence (AI) and big data era brought an unprecedented (and ever growing) need for fast and energy efficient computation that cannot be obtained with the classical von Neumann computing architecture. This paved the way to new technologies that try to mimic the human brain to leverage its energy efficient and distributed computing. Nonvolatile memory technologies seem to be the ideal solution for the hardware implementation of artificial neurons and synapses of Neural Network (NN) architectures and have been extensively investigated in the last years. However, they often suffer from limited linearity and symmetry, poor retention, and high variability, thus requiring significant advancements for their mass adoption in NNs. One of the cornerstones on which the required efforts must be based is certainly represented by device simulations, which can be effectively used to achieve a full understanding of the physics governing the device, which in turn is a pre-requisite for their design, optimization and successful exploitation in neuromorphic applications. In this scenario, we focus on Transition Metal Oxide (TMO)-based RRAM, Ferroelectric Tunnel Junctions (FTJ) and 3D-NAND Charge Trap devices and use simulations to address key issues related to neuromorphic operation (linearity and asymmetry) and reliability (variability and retention).

2022 - Variability and disturb sources in ferroelectric 3D NANDs and comparison to Charge-Trap equivalents [Relazione in Atti di Convegno]
Pesic, M.; Padovani, A.; Rollo, T.; Beltrando, B.; Strand, J.; Agrawal, P.; Shluger, A.; Larcher, L.
abstract

We investigate physical mechanisms driving the retention and disturb of charge-trap (CT) based and ferroelectric-(FE) based 3D NAND string. Combining a calibrated CT 3D NAND model and calibrated material properties of the FE material (extracted from FE-FinFET), we extrapolate and compare the existing workhorse with the low-power, high-speed contender. We show that: (1) a inherently discretized FE-stabilization combined with the polycrystalline nature of HZO, and interface charge compensation guarantees MLC capability; (2) FE 3D NAND offers higher ON currents that enable further Z-scaling. Furthermore, we develop a retention model and show that independently of the inherited discretization of the storage layer, lateral charge migration (of the parasitically trapped charge that stabilizes polarization) combined with pass voltage (disturb) can cause retention loss of FE 3D NAND. Finally, integration (layer-cut) and material engineering approaches are suggested for mitigation and guaranteeing stable operation of the string.

2021 - Analysis and Simulation of Interface Quality and Defect Induced Variability in MgO Spin-Transfer Torque Magnetic RAMs [Articolo su rivista]
Sikder, B.; Lim, J. H.; Kumar, M. A.; Padovani, A.; Haverty, M.; Kamal, U.; Raghavan, N.; Larcher, L.; Pey, K. -L.; Baten, M. Z.
abstract

Device-to-device variability of CoFeB/MgO based STT-MRAMs is studied based on experiments and simulations taking into account the influence of interface quality, temperature variation and device dimensionality. Metal-induced gap states resulting from electron transfer at the ferromagnet-tunnel barrier interface significantly influence the effective energy barrier height of these devices irrespective of their diameters. Switching voltage and parallel - antiparallel resistance values vary by as much as 43% and 30% respectively for about 13% variation of the energy barrier, whereas the tunneling magnetoresistance remains typically unaffected. WRITE cycles of highly scaled STT-MRAMs are therefore more susceptible to device-to-device variations resulting from microscopic variations in the interface quality, rather than the READ cycles. Such variations are observed to be independent of temperature, as well as spatial distribution of the defects.

2021 - Decoupling the sequence of dielectric breakdown in single device bilayer stacks by radiation-controlled, spatially localized creation of oxide defects [Articolo su rivista]
Aguirre, F. L.; Ranjan, A.; Raghavan, N.; Padovani, A.; Pazos, S. M.; Vega, N.; Muller, N.; Debray, M.; Molina-Reyes, J.; Pey, K. L.; Palumbo, F.
abstract

The breakdown (BD) sequence in high-K/interfacial layer (HK/IL) stacks for time-dependent dielectric breakdown (TDDB) has remained controversial for sub-45 nm CMOS nodes, as many attempts to decode it were not based on proper experimental methods. Know-how of this sequence is critical to the future design for reliability of FinFETs and nanosheet transistors. We present here the use of radiation fluence as a tool to precisely tune the defect density in the dielectric layer, which jointly with the statistical study of the soft, progressive and hard BD, allow us to infer the BD sequence using a single HfO2-SiOx bilayered MOS structure.

2021 - Extraction of Defects Properties in Dielectric Materials from I-V Curve Hysteresis [Articolo su rivista]
Torraca, P. L.; Caruso, F.; Padovani, A.; Spiga, S.; Tallarida, G.; Larcher, L.
abstract

Atomic defects in high-k materials affect the performance, reliability, variability, and scaling potential of electronic devices. Their characterization is thus of paramount importance, and methods exploiting electrical measurements are highly demanded. In this work we present a novel method for extracting the defect properties from I-V curve hysteresis measured at low electric field in thick metal-insulator-metal (MIM) stacks. The I-V curve hysteresis allows detecting the defects located near the electrode-insulator interfaces and aligned with the stack Fermi level, and extracting their properties. The defects are profiled cross-correlating the information provided by the low-field current hysteresis and the high-field steady-state current. This technique can be applied to MIM stacks fabricated in Back-End-of-Line for capacitors, embedded memories and thin film transistors.

2021 - Mechanism of Retention Degradation after Endurance Cycling of HfO2-based Ferroelectric Transistors [Abstract in Atti di Convegno]
Zhou, H.; Ocker, J.; Pesic, M.; Padovani, A.; Trentzsch, M.; Dunkel, S.; Muller, J.; Beyer, S.; Larcher, L.; Koushan, F.; Muller, S.; Mikolajick, T.
abstract

In this study, we provide insight into the mechanism of retention degradation after endurance cycling of HfO2-based ferroelectric field-effect transistors (FeFETs). Transfer characteristics of the FeFET are compared with the current-voltage response of the ferroelectric capacitors (FeCAP) for better understanding of the retention loss mechanism after cycling. Furthermore, a multiscale simulation by using the Ginestra™ modeling platform is conducted and the results show that charge trapping stabilizes the polarization switching and improves the retention behavior. Retention after cycling experiments are shown as well as pathways to reduce this degradation mechanism.

2021 - Toward Hole-Spin Qubits in Si p -MOSFETs within a Planar CMOS Foundry Technology [Articolo su rivista]
Bellentani, L.; Bina, M.; Bonen, S.; Secchi, A.; Bertoni, A.; Voinigescu, S. P.; Padovani, A.; Larcher, L.; Troiani, F.
abstract

Hole spins in semiconductor quantum dots represent a viable route for the implementation of electrically controlled qubits. In particular, the qubit implementation based on Si p-MOSFETs offers great potentialities in terms of integration with the control electronics and long-term scalability. Moreover, the future down scaling of these devices will possibly improve the performance of both the classical (control) and quantum components of such monolithically integrated circuits. Here, we use a multiscale approach to simulate a hole-spin qubit in a down-scaled Si-channel p-MOSFET, the structure of which is based on a commercial 22-nm fully depleted silicon-on-insulator device. Our calculations show the formation of well-defined hole quantum dots within the Si channel and the possibility of a general electrical control, with Rabi frequencies of the order of 100MHz for realistic field values. A crucial role of the channel aspect ratio is also demonstrated, as well as the presence of a favorable parameter range for the qubit manipulation.

2021 - Variability sources and reliability of 3D-FeFETs [Relazione in Atti di Convegno]
Pesic, M.; Beltrando, B.; Padovani, A.; Gangopadhyay, S.; Kaliappan, M.; Haverty, M.; Villena, M. A.; Piccinini, E.; Bertocchi, M.; Chiang, T.; Larcher, L.; Strand, J.; Shluger, A. L.
abstract

Discovery of ferroelectricity (FE) in binary oxides enables the advent of FE memories and a plethora of novel CMOS compatible building blocks spanning from the logic domain to high-density storage and neuromorphic computing. In this paper we develop the first comprehensive model of vertical Ferroelectric Field Effect Transistor, V-FeFET, to identify sources of variability, understand retention problems, and point a path to improving reliability and enabling high-density storage FE memories with extended endurance.

2020 - Application and benefits of target programming algorithms for ferroelectric HfO2transistors [Relazione in Atti di Convegno]
Zhou, H.; Ocker, J.; Padovani, A.; Pesic, M.; Trentzsch, M.; Dunkel, S.; Mulaosmanovic, H.; Slesazeck, S.; Larcher, L.; Beyer, S.; Muller, S.; Mikolajick, T.
abstract

The ferroelectric HfO2 based field effect transistor (FeFET) has been under research for many years and shows unique properties for applications in the field of emerging memories and in-memory computing. This work for the first time demonstrates how a target programming algorithm can improve the FeFET device characteristics with respect to endurance performance and variability for small device geometries. With this technique the threshold voltage Vt of the memory cell can be targeted to any desired value, which is essential for multilevel cells and analog in-memory computing as used in AI accelerators. The switching, trapping and detrapping characteristics of the cell and their influence on the target programming algorithm are presented. The trapping and leakage characteristics are modelled using the GinestraTM simulation software to extract the trap distribution in ferroelectric HfO2. Finally, a model for the underlying mechanism of the endurance degradation is proposed.

2020 - Engineering Atom Scale Defects in Materials for Future Electronic Devices [Relazione in Atti di Convegno]
Pramanik, D.; Nardi, F.; Padovani, A.
abstract

A multiscale simulation platform predicts the effect of atomic level defects in thin films on the electrical characteristics of nanoscale devices and identifies ways to engineer these defects to achieve optimum performance and reliability in logic and memory circuits.

2020 - Multiscale modeling of CeO2/La2 O3 stacks for material/defect characterization [Relazione in Atti di Convegno]
Dianat, B.; Padovani, A.; Larcher, L.
abstract

Presence of defects in high-k dielectric materials will affect device's electrical properties, thus, defect/material characterization is of great importance. We present a simulation-based methodology relying on an accurate description of charge trapping and transport that is useful to extract relevant information on material and defect characteristics. This methodology was applied to cerium oxide and lanthanum oxide high-k dielectric materials and as a result, material properties alongside defect characteristics were extracted. Consequently, main charge conduction mechanism was identified to be trap-assisted tunneling (TAT).

2019 - A Sensitivity Map-Based Approach to Profile Defects in MIM Capacitors From I-V, C-V, and G-V Measurements [Articolo su rivista]
Padovani, A.; Kaczer, B.; Pesic, M.; Belmonte, A.; Popovici, M.; Nyns, L.; Linten, D.; Afanas'Ev, V. V.; Shlyakhov, I.; Lee, Y.; Park, H.; Larcher, L.
abstract

We present a defect spectroscopy technique to profile the energy and spatial distribution of defects within a material stack from leakage current (J-V), capacitance (C-V), and conductance (G-V) measurements. The technique relies on the concept of sensitivity maps (SMs) that identify the bandgap regions, where defects affect those electrical characteristics. The information provided by SMs are used to reproduce J-V, C-V, and G-V data measured at different temperatures and frequencies by means of physics-based simulations relying on an accurate description of carrier-defect interactions. The proposed defect spectroscopy technique is applied to ZrO2-based metal-insulator-metal structures of different compositions for dynamic random-access memory capacitor applications. The origin of the observed voltage, temperature, and frequency dependencies of the I-V, C-V, and G-V data is understood, and the atomic structure of the relevant stack defects is identified.

2019 - Advanced modeling and characterization techniques for innovative memory devices: The RRAM case [Capitolo/Saggio]
Puglisi, Francesco Maria; Padovani, Andrea; Pavan, Paolo; Larcher, Luca
abstract

2019 - Boron Vacancies Causing Breakdown in 2D Layered Hexagonal Boron Nitride Dielectrics [Articolo su rivista]
Ranjan, A.; Raghavan, N.; Puglisi, F. M.; Mei, S.; Padovani, A.; Larcher, L.; Shubhakar, K.; Pavan, P.; Bosman, M.; Zhang, X. X.; O'Shea, S. J.; Pey, K. L.
abstract

Dielectric breakdown in 2D insulating films for future logic device technology is not well understood yet, in contrast to the extensive insight we have in the breakdown of bulk dielectric films, such as HfO2 and SiO2. In this letter, we investigate the stochastic nature of breakdown (BD) in hexagonal boron nitride (h-BN) films using ramp voltage stress and examine the BD trends as a function of stress polarity, area, and temperature. We present evidence that points to a non-Weibull distribution for h-BN BD and use the multi-scale physics-based simulations to extract the energetics of the defects that are precursors to BD, which happens to be boron vacancies.

2019 - Deconvoluting charge trapping and nucleation interplay in FeFETs: Kinetics and Reliability [Relazione in Atti di Convegno]
Pesic, M.; Padovani, A.; Slcsazeck, S.; Mikolajick, T.; Larcher, L.
abstract

Discovery of ferroelectric (FE) behavior in HfO 2 removed the compatibility roadblocks between the state-of-the-art CMOS and FE memories. Even though FE FETs (FeFETs) are scaled into 22 nm nodes and beyond, the limits of the technology as well as the physical mechanisms and reliability are still under research. In this paper we successfully developed a multiscale modeling platform to understand the interplay between the FE switching and charge trapping. Starting from the nucleation theory and rigorous charge transport modeling we present for the first time a self-consistent modeling framework we used for investigation of reliability and variability in FeFETs.

2019 - Investigating the Statistical-Physical Nature of MgO Dielectric Breakdown in STT-MRAM at Different Operating Conditions [Relazione in Atti di Convegno]
Lim, J. H.; Raghavan, N.; Padovani, A.; Kwon, J. H.; Yamane, K.; Yang, H.; Naik, V. B.; Larcher, L.; Lee, K. H.; Pey, K. L.
abstract

Ultra-thin dielectric breakdown (BD) has been studied in-depth for SiO 2 and HfO 2 in CMOS devices in the past. In general, the degradation physics and model governing BD in these materials are assumed to hold true for MgO. This study provides evidences that this assumption may not be true by investigating in detail the statistical nature of BD in MgO dielectrics for wide range of operating conditions, relevant to its application as spin transfer torque magnetic random access memory (STT-MRAM). Our analysis shows that - MgO BD is polarity dependent; lifetime is lower for bipolar (AC) stress; defect generation is clustered in space and time; self-heating dominates for low frequencies; temperature within the percolation path exhibits fast transients (thermal runaway); Weibull model does not apply to BD statistics and defect generation (F + ) is charge fluence driven (and field assisted) with power law model being most suited for lifetime extrapolation.

2019 - Investigation of I-V linearity in TaO x -Based RRAM devices for neuromorphic applications [Articolo su rivista]
Sung, C.; Padovani, A.; Beltrando, B.; Lee, D.; Kwak, M.; Lim, S.; Larcher, L.; Della Marca, V.; Hwang, H.
abstract

We perform experiments and device simulations to investigate the origin of current-voltage (I-V) linearity of TaO x -based resistive switching memory (RRAM) devices for their possible application as electronic synapses. By using electrical characterization and simulations, we link the electrical characteristics (linear or nonlinear I-V) to the microscopic properties of the conductive filament (CF). Our findings indicate that the shape and the thermal properties of the CF region are crucial to achieve linear I-V characteristics. These results allow optimizing the I-V curve linearity of TaO x -based RRAM devices, explaining the wide range of linear I-V characteristics experimentally observed on RRAM device obtained. When weight sum operation using SPICE simulations is performed, the read current is improved under the condition of linear I-V characteristics due to current loss minimization.

2019 - Multiscale modeling for application-oriented optimization of resistive random-access memory [Articolo su rivista]
La Torraca, P.; Puglisi, F. M.; Padovani, A.; Larcher, L.
abstract

Memristor-based neuromorphic systems have been proposed as a promising alternative to von Neumann computing architectures, which are currently challenged by the ever-increasing computational power required by modern artificial intelligence (AI) algorithms. The design and optimization of memristive devices for specific AI applications is thus of paramount importance, but still extremely complex, as many dierent physical mechanisms and their interactions have to be accounted for, which are, in many cases, not fully understood. The high complexity of the physical mechanisms involved and their partial comprehension are currently hampering the development of memristive devices and preventing their optimization. In this work, we tackle the application-oriented optimization of Resistive Random-Access Memory (RRAM) devices using a multiscale modeling platform. The considered platform includes all the involved physical mechanisms (i.e., charge transport and trapping, and ion generation, diusion, and recombination) and accounts for the 3D electric and temperature field in the device. Thanks to its multiscale nature, the modeling platform allows RRAM devices to be simulated and the microscopic physical mechanisms involved to be investigated, the device performance to be connected to the material's microscopic properties and geometries, the device electrical characteristics to be predicted, the effect of the forming conditions (i.e., temperature, compliance current, and voltage stress) on the device's performance and variability to be evaluated, the analog resistance switching to be optimized, and the device's reliability and failure causes to be investigated. The discussion of the presented simulation results provides useful insights for supporting the application-oriented optimization of RRAM technology according to specific AI applications, for the implementation of either non-volatile memories, deep neural networks, or spiking neural networks.

2019 - Recommended Methods to Study Resistive Switching Devices [Articolo su rivista]
Lanza, Mario; Wong, H. -S. Philip; Pop, Eric; Ielmini, Daniele; Strukov, Dimitri; Regan, Brian C.; Larcher, Luca; Villena, Marco A.; Yang, J. Joshua; Goux, Ludovic; Belmonte, Attilio; Yang, Yuchao; Puglisi, Francesco M.; Kang, Jinfeng; Magyari-Köpe, Blanka; Yalon, Eilam; Kenyon, Anthony; Buckwell, Mark; Mehonic, Adnan; Shluger, Alexander; Li, Haitong; Hou, Tuo-Hung; Hudec, Boris; Akinwande, Deji; Ge, Ruijing; Ambrogio, Stefano; Roldan, Juan B.; Miranda Castellano, Enrique Alberto; Suñe, Jordi; Pey, Kin Leong; Wu, Xing; Raghavan, Nagarajan; Wu, Ernest; Lu, Wei D.; Navarro, Gabriele; Zhang, Weidong; Wu, Huaqiang; Li, Runwei; Holleitner, Alexander; Wurstbauer, Ursula; Lemme, Max C.; Liu, Ming; Long, Shibing; Liu, Qi; Lv, Hangbing; Padovani, Andrea; Pavan, Paolo; Valov, Ilia; Jing, Xu; Han, Tingting; Zhu, Kaichen; Chen, Shaochuan; Hui, Fei; Shi, Yuanyuan
abstract

Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, with electronic nonvolatile memories being those that have received the most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology.

2019 - Role of Defects in the Reliability of HfO2/Si-Based Spacer Dielectric Stacks for Local Interconnects [Relazione in Atti di Convegno]
Wu, C.; Chasin, A.; Padovani, A.; Lesniewska, A.; Demuynck, S.; Croes, K.
abstract

MIM planar capacitors with different spacer dielectrics (SiN, SiCO and SiCBN) of varying thickness deposited on a 2nm Hf02 gate dielectric, were fabricated to investigate the gate/spacer stack intrinsic electrical reliability performance. The polarity dependent leakage current of gate/spacer dielectric stacks is understood by employing band diagram analyses and simulations using the Ginestra™ software. The asymmetrical J-E characteristic of the Hf02/SiN dielectric stack is attributed to the presence of a high defect density in the Hf02/SiN interface region originating from the deposition process. On the other hand, the higher as-grown defect density in SiCO and SiCBN results in a symmetrical J-E characteristic. A low defect generation efficiency in the thin SiN stacks has been demonstrated using stress induced leakage current and charge to breakdown studies. The underlying mechanisms can be linked to a change in degradation mechanism from electronic excitation to electron induced vibrational excitation, which is valid for low defect density dielectric systems. To ensure low leakage currents and robust dielectric breakdown characteristics for ultra-thin spacer layers below 5nm, it is important to control defect densities below 1019cm-3ev-1in the film.

2019 - Spatio-Temporal Defect Generation Process in Irradiated HfO2 MOS Stacks: Correlated Versus Uncorrelated Mechanisms [Relazione in Atti di Convegno]
Aguirre, F. L.; Padovani, A.; Ranjan, A.; Raghavan, N.; Vega, N.; Muller, N.; Matias Pazos, S.; Debray, M.; Molina, J.; Pey, K. L.; Palumbo, F.
abstract

In this paper, we analyze the dependence of the Weibull slope (ß) extracted from TDDB tests on HfO2 MOS capacitors (MOSCAPs) on the initial density of defects artificially induced by carefully tuned micro beam irradiation experiments with different carbon dosages. The consistent experimental trend of reducing $p$ with increasing defect density was reproducible only with physics-based breakdown simulations that considered correlated defect generation in HfO2 and localized damage (partial percolation paths) traces created by the impinging ions. Scenarios of spatially random initial defect distribution and random stress-induced defect generation (in space and time) could not explain the experimental trends, confirming that correlated defect generation does exist in HfO2 thereby altering the conventional understanding of TDDB by quite a bit.

2019 - Statistical Simulation to Predict Variability of TANOS Program/Erase Characteristics for Non-Volatile Memory Applications [Relazione in Atti di Convegno]
Baten, M. Z.; Kumar, M. A.; Padovani, A.; Larcher, L.; Pramanik, D.
abstract

The impact of device-to-device statistical variation on Program/Erase (P/E) transients of planar TANOS devices is investigated using a multi-scale simulation approach. Atomic-level material and defect properties are first extracted from experimental results and then employed to study variability of the flat-band voltage shift. Erase characteristics are observed to be more affected by statistical variation. Interestingly, by adjusting temperature, gate voltage and/or blocking layer thickness, an optimized operating condition can be reached such that variability in 3D TANOS arrays is minimized.

2019 - Understanding and Variability of Lateral Charge Migration in 3D CT-NAND Flash with and Without Band-Gap Engineered Barriers [Relazione in Atti di Convegno]
Padovani, A.; Pesic, M.; Kumar, M. A.; Blomme, P.; Subirats, A.; Vadakupudhupalayam, S.; Baten, Z.; Larcher, L.
abstract

3D NAND Flash represents the unmatchable non- volatile memory concerning the bit-cost scaling efficiency and a role model for all emerging memories. Yet some reliability features of these devices i.e. quantification of the threshold voltage shift due to the lateral and vertical migration/loss of charges (LCL and VCL, respectively) is not fully understood. In this study we use a multi-scale modeling approach start from identification of the defects responsible for the charge trapping and quantify the LCL and VLC. As a part of engineering of the barrier we investigate also band-gap engineered (BGE) devices. We show that LCL dominates the charge loss during the retention and that highest portion of injected charge ends up in Al2O3 layer of BGE device.

2019 - Understanding the Impact of Annealing on Interface and Border Traps in the Cr/HfO2/Al2O3/MoS2 System [Articolo su rivista]
Zhao, Peng; Padovani, Andrea; Bolshakov, Pavel; Khosravi, Ava; Larcher, Luca; Hurley, Paul K.; Hinkle, Christopher L.; Wallace, Robert M.; Young, Chadwin D.
abstract

Top-gated, few-layer MoS2 transistors with HfO2 (6 nm)/Al2O3 (3 nm) gate dielectric stacks are fabricated and electrically characterized by capacitance-voltage (C-V) measurements to study electrically active traps (D-it) in the vicinity of the Al2O3/MoS2 interface. Devices with low D-it and high D-it are both observed in C-V characterization, and the impact of H-2/N-2 forming gas annealing at 300 and 400 degrees C on the D-it density and distribution is studied. A 300 degrees C anneal is able to reduce the D-it significantly, while the 400 degrees C anneal increases defects in the gate stack. Simulation with modeled defects suggests a sizable decrease in D-it, half the amount of positive fixed charge in the dielectric, and slightly increased unintentional doping in MoS2 after a 300 degrees C anneal. In the as-fabricated devices displaying high D-it levels, the energy distribution of the D-it located at the Al2O3/MoS2 interface is continuous from the conduction band edge of MoS2 down to 0.13-0.35 eV below the conduction band edge. A plausible D-it origin in our experiments could come from the unexpected oxygen atoms that fill the sulfur vacancies during the UV-O-3 functionalization treatment. The border trap concentration in Al2O3 is the same, both before and after the anneal, suggesting a different origin of the border traps, possibly due to the low-temperature atomic-layer-deposited process.

2018 - Defect spectroscopy from electrical measurements: A simulation based technique [Relazione in Atti di Convegno]
Larcher, L.; Padovani, A.; Pramanik, D.; Kaczer, B.; Palumbo, F.
abstract

We present in this paper a novel defect spectroscopy technique for extracting defect and material properties of gate oxides and dielectrics used for memory devices (e.g. DRAM, RRAM). The method is based on the correlate simulation of electrical characteristics (IV, CV, GV, BTI), to allow the determination of the energy distribution and depth profile of atomic defects within the material bandgap. This novel defect spectroscopy technique is applied to MOSFET gate stacks with Si and InGaAs, and to DRAM capacitors.

2018 - Extracting Atomic Defect Properties From Leakage Current Temperature Dependence [Articolo su rivista]
Larcher, Luca; Padovani, Andrea; Puglisi, Francesco Maria; Pavan, Paolo
abstract

In modern electronic devices, a variety of novel materials have been introduced such as transition metal oxides, chalcogenides, ferroelectric, and magnetic materials. The electrical response of such materials, used also as active layers, is strongly affected by atomic defects, which affect device performances, variability, and reliability. Extracting the defect properties (i.e., density, energy, and atomic nature) is, thus, crucial to both engineer the performances of electron devices and correctly project their scaling potential and reliability. In this paper, we propose a simple method to extract the atomic properties of defects from the thermal activation energy of the leakage current using a charge trapping relaxation model.

2018 - Multiscale modeling of neuromorphic computing: From materials to device operations [Relazione in Atti di Convegno]
Larcher, L.; Padovani, A.; Di Lecce, V.
abstract

In this paper, a multiscale modeling platform for neuromorphic computing devices connecting the atomic material properties to the electrical device performances is presented. The main ingredients of the modeling platform are discussed in view of the different technologies (e.g. RRAM, PCM, FTJ) proposed for 3D integrated neuromorphic computing.

2018 - Random telegraph noise in 2D hexagonal boron nitride dielectric films [Articolo su rivista]
Ranjan, A.; Puglisi, F. M.; Raghavan, N.; O'Shea, S. J.; Shubhakar, K.; Pavan, P.; Padovani, A.; Larcher, L.; Pey, K. L.
abstract

This study reports the observation of low frequency random telegraph noise (RTN) in a 2D layered hexagonal boron nitride dielectric film in the pre- and post-soft breakdown phases using conductive atomic force microscopy as a nanoscale spectroscopy tool. The RTN traces of the virgin and electrically stressed dielectric (after percolation breakdown) were compared, and the signal features were statistically analyzed using the Factorial Hidden Markov Model technique. We observe a combination of both two-level and multi-level RTN signals in h-BN, akin to the trends commonly observed for bulk oxides such as SiO2 and HfO2. Experimental evidence suggests frequent occurrence of unstable and anomalous RTN traces in 2D dielectrics which makes extraction of defect energetics challenging.

2018 - Role of electron and hole trapping in the degradation and breakdown of SiO2 and HfO2 films [Relazione in Atti di Convegno]
Gao, D. Z.; Strand, J.; El-Sayed, A. -M.; Shluger, A. L.; Padovani, A.; Larcher, L.
abstract

We investigated possible mechanisms for correlated defect production in amorphous (a) SiO2 and HfO2 films under applied stress bias using ab initio simulations. During bias application, electron injection into these films may lead to the localization of up to two electrons at intrinsic trapping sites which are present due to the natural structural disorder in amorphous structures. Trapping two electrons weakens Si-O and Hf-O bonds to such an extent that the thermally activated creation of Frenkel defects, O vacancies and O2- interstitial ions, becomes efficient even at room temperature. Bias application affects defect creation barriers and O2- interstitial diffusion. The density of trapping sites is different in a-SiO2 and a-HfO2. This leads to qualitatively different degradation kinetics, which results from different correlation in defect creation in the two materials. These effects affect TDDB statistics and its dependence on the film thickness.

2018 - Time-dependent dielectric breakdown statistics in SiO2 and HfO2 dielectrics: Insights from a multi-scale modeling approach [Relazione in Atti di Convegno]
Padovani, A.; Larcher, L.
abstract

We use a multi-scale modeling framework to investigate time dependent dielectric breakdown (TDDB) distributions in SiO2-and HfO2-based stacks. We show that the low and thickness independent Weibull slope (β) observed in HfO2 is due to the high intrinsic defect density and to the spatial correlation of the defect generation process. We investigate the origin of the double slope observed on TDDB distributions in IL-HfO2 stacks: we have found that it is related to the stochastic nature of the bond-breakage process. This is important for a correct evaluation of the lifetime of logic devices.

2018 - Understanding and Optimization of Pulsed SET Operation in HfOx-Based RRAM Devices for Neuromorphic Computing Applications [Articolo su rivista]
Padovani, A.; Woo, J.; Hwang, H.; Larcher, L.
abstract

We use experiments and device simulations to investigate pulsed SET operation of HfO2-based RRAM devices for their possible use as electronic synapses. The application of a train of identical pulses only allows for an abrupt change of the device current, which is not suitable for synaptic devices. By using simulations, we link the microscopic properties and changes of the conductive filament during the pulsed operation to the measured conductance and its dependence on pulse voltage, width, and number. The results allow us to derive guidelines that we use to design optimized SET pulses (or pulse trains) allowing extending the conventional binary operation of HfO2-based RRAMs to the multi-level cell operation required by electronic synapses.

2017 - A microscopic mechanism of dielectric breakdown in SiO2films: An insight from multi-scale modeling [Articolo su rivista]
Padovani, A.; Gao, D. Z.; Shluger, A. L.; Larcher, L.
abstract

Despite extensive experimental and theoretical studies, the atomistic mechanisms responsible for dielectric breakdown (BD) in amorphous (a)-SiO2are still poorly understood. A number of qualitative physical models and mathematical formulations have been proposed over the years to explain experimentally observable statistical trends. However, these models do not provide clear insight into the physical origins of the BD process. Here, we investigate the physical mechanisms responsible for dielectric breakdown in a-SiO2using a multi-scale approach where the energetic parameters derived from a microscopic mechanism are used to predict the macroscopic degradation parameters of BD, i.e., time-dependent dielectric breakdown (TDDB) statistics, and its voltage dependence. Using this modeling framework, we demonstrate that trapping of two electrons at intrinsic structural precursors in a-SiO2is responsible for a significant reduction of the activation energy for Si-O bond breaking. This results in a lower barrier for the formation of O vacancies and allows us to explain quantitatively the TDDB data reported in the literature for relatively thin (3-9 nm) a-SiO2oxide films.

2017 - A multiscale modeling approach for the simulation of OxRRAM devices [Relazione in Atti di Convegno]
Padovani, A.; Larcher, L.; Woo, J.; Hwang, H.
abstract

We present a multiscale modeling platform that exploits ab-initio calculation results and a material-related description of the most relevant defect-related phenomena in dieledtrics (charge trapping and transport, degradation and atomic species motion) to interpret and understand the electrical characteristics of OxRAM memory devices for non-volatile memories and neuromorphic applications. Simulation results provide a deep and quantitative understanding of the factors controlling device operation. The proposed multiscale modeling platform represents a powerful tool for investigating material properties and optimizing device performances and reliability.

2017 - Correlated Effects on Forming and Retention of Al Doping in HfO2-Based RRAM [Articolo su rivista]
Alayan, Mouhamad; Vianello, Elisa; De Salvo, Barbara; Perniola, Luca; Padovani, Andrea; Larcher, Luca
abstract

Editor's note: Retention time is one of the key parameters of emerging memories, which define the time duration the data can be retained when the power supply is removed. In this work, the authors investigate the forming voltage and the data retention of aluminum (Al)-doped HfO2-based RRAM devices and suggest a way to improve the device's data retention time. - - Yiran Chen, Duke University

2017 - Linking Conductive Filament Properties and Evolution to Synaptic Behavior of RRAM Devices for Neuromorphic Applications [Articolo su rivista]
Woo, Jiyong; Padovani, Andrea; Moon, Kibong; Kwak, Myounghun; Larcher, Luca; Hwang, Hyunsang
abstract

We perform a comparative study of HfO2 and Ta2O5 resistive switching memory (RRAM) devices for their possible application as electronic synapses. By means of electrical characterization and simulations, we link their electrical behavior (digital or analog switching) to the properties and evolution of the conductive filament (CF). More specifically, we identify that bias-polarity-dependent digital switching in HfO2 RRAM is primarily related to the creation and rupture of an oxide barrier. Conversely, the modulation of the CF size in Ta2O5 RRAM allows bias-polarity-independent analog switching with multiple states. Therefore, when the Ta2O5 RRAM is used to implement a synapse in multilayer perceptron neural networks operated by back-propagation algorithms, patterns in handwritten digits can be recognized with high accuracy.

2017 - Localized characterization of charge transport and random telegraph noise at the nanoscale in HfO2 films combining scanning tunneling microscopy and multi-scale simulations [Articolo su rivista]
Thamankar, R.; Puglisi, Francesco Maria; Ranjan, A.; Raghavan, N.; Shubhakar, K.; Molina, J.; Larcher, Luca; Padovani, Andrea; Pavan, Paolo; O'Shea, S. J.; Pey, K. L.
abstract

Charge transport and Random Telegraph Noise (RTN) are measured successfully at the nanoscale on a thin polycrystalline HfO2 film using room temperature Scanning Tunneling Microscopy (STM). STM is used to scan the surface of the sample with the aim of identifying grains and grain boundaries, which show different charge transport characteristics. The defects responsible for charge transport in grains and grain boundaries are identified as positively charged oxygen vacancies by matching the localized I-V curves measured at the nanoscale with the predictions of physics-based multi-scale simulations. The estimated defect densities at grains and grain boundaries agree with earlier reports in the literature. Furthermore, the current-time traces acquired by STM at fixed bias voltages on grains show characteristic RTN fluctuations. The high spatial resolution of the STM-based RTN measurement allows us to detect fluctuations related to individual defects that typically cannot be resolved by the conventional device-level probe station measurement. The same physical framework employed to reproduce the I-V conduction characteristics at the grains also successfully simulates the RTN detected at the nanoscale. We confirm that charge trapping at defects not directly involved in charge transport can induce significant current fluctuations through Coulombic interactions with other defects in the proximity that support charge transport.

2017 - Multiscale modeling of defect-related phenomena in high-k based logic and memory devices [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Puglisi, Francesco Maria; Pavan, Paolo
abstract

We present a multiscale modeling platform that exploits ab-initio calculation results and a material-related description of the most relevant defect-related phenomena in dielectrics (charge trapping and transport, degradation and atomic species motion) to interpret the reliability and electrical characteristics of logic and memory devices. The model is used to identify and characterize the dielectric defects responsible for the charge transport and degradation in SiOx/high-k (HK) bi-layer logic devices and to investigate the kinetics of forming and switching operations of Hf-based RRAM memories. Simulation results provide a deep and quantitative understanding of the factors controlling device operation and reliability. The proposed multiscale modeling platform represents a powerful tool for investigating material properties and optimizing device performances and reliability.

2017 - Multiscale modeling of oxide RRAM devices for memory applications: from material properties to device performance [Articolo su rivista]
Larcher, Luca; Padovani, Andrea
abstract

RRAM devices have been subjected to intense research efforts and are proposed for nonvolatile memory and neuromorphic applications. In this paper we describe a multiscale modeling platform connecting the microscopic properties of the resistive switching material to the electrical characteristics and operation of RRAM devices. The platform allows self-consistently modeling the charge and ion transport and the material structural modifications occurring during RRAM operations and reliability, i.e., conductive filament creation and partial disruption. It allows describing the electrical behavior (current, forming, switching, cycling, reliability tests) of RRAM devices in static and transient conditions and their dependence on external conditions (e.g., temperature). Thanks to the kinetic Monte Carlo approach, the inherent variability of physical processes is properly accounted for. Simulation results can be used both to investigate material properties (including atomic defect distributions) and to optimize stack and bias pulses for optimum device performances and reliability.

2017 - Random telegraph noise: Measurement, data analysis, and interpretation [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

Abstract: In this paper, we delve into one of the most relevant defects-related phenomena causing failures in the operation of modern nanoscale electron devices, namely Random Telegraph Noise (RTN). Due to its detrimental impact on devices and circuits performances, RTN mechanism must be thoroughly understood, which requires establishing a self-consistent framework encompassing automated measurement techniques, data analysis algorithms, and physics-based modeling. This platform is not only required to understand the physics of RTN-related failures, but also to enable RTN analysis as a tool to investigate device reliability. Starting from the analysis of RTN signal statistical properties, we propose a set of guidelines to perform correct RTN measurements and data analysis, in order to get reliable results that are needed for an unbiased physical interpretation. This is achieved by combining automated experiments with sophisticated data analysis, consistency check, and comprehensive physics-based simulations. RTN analysis is then applied to two different devices for logic and memory applications, respectively: FinFETs and RRAMs. Particularly, the analysis of the statistical properties of RTN simultaneously measured on the drain and on the gate current of FinFETs allows understanding the details of the defects generation during stress. The analysis of RTN measured during the read operation in RRAM devices allows understanding the physical origin of RTN in these devices and identifying the defects species involved in this phenomenon.

2017 - Scaling perspective and reliability of conductive filament formation in ultra-scaled HfO2 Resistive Random Access Memory [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Celano, Umberto; Padovani, Andrea; Vandervorst, Wilfried; Larcher, Luca; Pavan, Paolo
abstract

In this paper we report about the scaling perspective of ultra-scaled HfO2 Resistive Random Access Memory devices. Due to filamentary conduction, the scalability of these devices is considered to be ultimately limited by the size of the conductive filament. However, even though the precise size and shape of the filament is not fully elucidated, it is widely accepted that its size is mainly controlled by the current compliance. In turn, the latter sets the operating current level of the cell. The reduction of the current level is nevertheless accompanied by performance instabilities, which are the main reliability threat for low-current operations. The resulting tradeoff raises concerns about the scalability potential of RRAM devices. In this work, we combine device-level measurements, Conductive Atomic-Force Microscopy (C-AFM), and physics-based simulations of HfO2 RRAM devices to elucidate the reason for these instabilities. Results clarify the scaling perspectives of ultra-low cell size (< 10×10 nm2) RRAMs and their reliability.

2017 - Self-rectifying behavior and analog switching under identical pulses using Tri-layer RRAM crossbar array for neuromorphic systems [Relazione in Atti di Convegno]
Alayan, M.; Vianello, E.; Larcher, L.; Padovani, A.; Levisse, A.; Castellani, N.; Charpin, C.; Bernasconi, S.; Molas, G.; Portal, J. M.; De Salvo, B.; Perniola, L.
abstract

This work analyzes the self-rectifying behavior and the response under identical pulses of tri-layer RRAMs in crossbar arrays to implement the synapse function. Our finding shows that tri-layer RRAMs allow to achieve a stable Low Resistance State (LRS) without complete oxide breakdown. The first RRAM layer works as tunneling barrier allowing to achieve on-state half-bias nonlinearity. Thanks to LRS nonlinearity the power consumption during synaptic programming is reduces of one order of magnitude. Analog switching under identical pulses allows to emulate synaptic plasticity. The multilevel states of conductance have been explained by the enlargement of the conductive filament (CF) in the broken oxide by means of physical based simulations.

2016 - Anomalous random telegraph noise and temporary phenomena in resistive random access memory [Articolo su rivista]
Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper we present a comprehensive examination of the characteristics of complex Random Telegraph Noise (RTN) signals in Resistive Random Access Memory (RRAM) devices with TiN/Ti/HfO2/TiN structure. Initially, the anomalous RTN (aRTN) is investigated through careful systematic experiment, dedicated characterization procedures, and physics-based simulations to gain insights into the physics of this phenomenon. The experimentally observed RTN parameters (amplitude of the current fluctuations, capture and emission times) are analyzed in different operating conditions. Anomalous behaviors are characterized and their statistical characteristics are evaluated. Physics-based simulations considering both the Coulomb interactions among different defects in the device and the possible existence of defects with metastable states are exploited to suggest a possible physical origin of aRTN. The same simulation framework is also shown to be able to predict other temporary phenomena related to RTN, such as the temporary change in RTN stochastic properties or the sudden and iterative random appearing and vanishing of RTN fluctuations always exhibiting the same statistical characteristics. Results highlight the central role of the electrostatic interactions among individual defects and the trapped charge in describing RTN and related phenomena.

2016 - Bipolar Resistive RAM Based on HfO2: Physics, Compact Modeling, and Variability Control [Articolo su rivista]
Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper, we thoroughly investigate the characteristics of the TiN/Ti/HfO/TiN resistive random access memory (RRAM) device. The physical mechanisms involved in the device operations are comprehensively explored from the atomistic standpoint. Self-consistent physics simulations based on a multi-scale approach are employed to achieve a complete understanding of the device physics. The latter includes different charge and ion transport phenomena, as well as structural modifications occurring during the device operations. The main sources of variability are also included by connecting the electrical response of the device to the atomistic material properties. The detailed understanding of the device physics allows developing a physics-based compact model describing the device switching in different operating conditions, including also the effects of cycling variability. Random telegraph noise (RTN), which constitutes an additional variability source, and its relations with cycling variability are analyzed. A statistical link between the programmed resistance and the worst-case RTN effect is found and exploited to include RTN effects in the compact model. Finally, we show how implementing an advanced programming scheme tailored on the device physics allows optimal control over variability and RTN, eventually achieving reliable and RTN-resilient two-bits/cell operations.

2016 - Electrical defect spectroscopy and reliability prediction through a novel simulation-based methodology [Relazione in Atti di Convegno]
Larcher, Luca; Sereni, Gabriele; Padovani, Andrea; Vandelli, Luca
abstract

The semiconductor technology development requires a full understanding of material implications at the device level. This requires connecting the microscopic/atomic properties of the material (e.g. defect) to the macroscopic electrical characteristics of the device. In this scenario, we developed a new methodology, supported by a multi-scale modeling and simulation (MS) software [1], [2], which allows extracting from the simulations of the electrical characterization measurements (I-V, C-V, G-V, BTI, Charge-Pumping, noise, stress) the material and device properties that can be used for the technology development, the design of novel devices and the analysis of the device reliability also at statistical level (TDDB, leakage currents), Fig. 1.

2016 - Moving graphene devices from lab to market: Advanced graphene-coated nanoprobes [Articolo su rivista]
Hui, F.; Vajha, P.; Shi, Y.; Ji, Y.; Duan, H.; Padovani, A.; Larcher, L.; Li, X. R.; Xu, J. J.; Lanza, M.
abstract

After more than a decade working with graphene there is still a preoccupying lack of commercial devices based on this wonder material. Here we report the use of high-quality solution-processed graphene sheets to fabricate ultra-sharp probes with superior performance. Nanoprobes are versatile tools used in many fields of science, but they can wear fast after some experiments, reducing the quality and increasing the cost of the research. As the market of nanoprobes is huge, providing a solution for this problem should be a priority for the nanotechnology industry. Our graphene-coated nanoprobes not only show enhanced lifetime, but also additional unique properties of graphene, such as hydrophobicity. Moreover, we have functionalized the surface of graphene to provide piezoelectric capability, and have fabricated a nano relay. The simplicity and low cost of this method, which can be used to coat any kind of sharp tip, make it suitable for the industry, allowing production on demand.

2016 - Multiscale modeling of electron-ion interactions for engineering novel electronic device and materials [Relazione in Atti di Convegno]
Larcher, Luca; Puglisi, Francesco Maria; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo
abstract

In this work, we present a multiscale simulation platform as a viable tool to engineer novel electron devices. The tool connects the specific material properties (as atomic defects, interfaces, material morphology) to the electrical behavior of the device, representing a virtual space for the design of novel electrons device purposely exploiting atom-electron interactions. This simulation platform is based on the modeling the microscopic interactions and chemical reactions (e.g. bond breaking) between electrons and atomic species (ions, vacancies, dangling bonds). In this work, we show how this tool can be used to design resistive memory devices based on binary oxides. The fundamental importance of the complex interplay between charge carriers and atomic species is highlighted by showing how these interactions determine many electrical characteristics of the device, including charge transport, structural modifications associated with resistive switching, variability, and noise fluctuations.

2016 - Multiscale modeling of electron-ion interactions for engineering novel electronic devices and materials [Relazione in Atti di Convegno]
Larcher, Luca; Puglisi, Francesco Maria; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo
abstract

In this work, we present a multiscale simulation platform as a viable tool to engineer novel electron devices. The tool connects the specific material properties (as atomic defects, interfaces, material morphology) to the electrical behavior of the device, representing a virtual space for the design of novel electrons device purposely exploiting atom-electron interactions. This simulation platform is based on the modeling the microscopic interactions and chemical reactions (e.g. bond breaking) between electrons and atomic species (ions, vacancies, dangling bonds). In this work, we show how this tool can be used to design resistive memory devices based on binary oxides. The fundamental importance of the complex interplay between charge carriers and atomic species is highlighted by showing how these interactions determine many electrical characteristics of the device, including charge transport, structural modifications associated with resistive switching, variability, and noise fluctuations.

2016 - Operations, Charge Transport, and Random Telegraph Noise in HfOx Resistive Random Access Memory: a Multi-scale Modeling Study [Articolo su rivista]
Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this work we explore the mechanisms responsible for Random Telegraph Noise (RTN) fluctuations in HfOx Resistive Random Access Memory (RRAM) devices. The statistical properties of the RTN are analyzed in many operating conditions exploiting the Factorial Hidden Markov Model (FHMM) to decompose the multilevel RTN traces in a superposition of two-level fluctuations. This allows the simultaneous characterization of individual defects contributing to the RTN. Results, together with multi-scale physics-based simulations, allows thoroughly investigating the physical mechanisms which could be responsible for the RTN current fluctuations in the two resistive states of these devices, including also the charge transport features in a comprehensive framework. We consider two possible options, which are the Coulomb blockade effect and the possible existence of metastable states for the defects assisting charge transport. Results indicate that both options may be responsible for RTN current fluctuations in HRS, while RTN in LRS is attributed to the temporary screening effect of the charge trapped at defect sites around the conductive filament.

2016 - Physical Mechanisms behind the Field-Cycling Behavior of HfO2-Based Ferroelectric Capacitors [Articolo su rivista]
Pesic, Milan; Fengler, Franz Paul Gustav; Larcher, Luca; Padovani, Andrea; Schenk, Tony; Grimley, Everett D.; Sang, Xiahan; Lebeau, James M.; Slesazeck, Stefan; Schroeder, Uwe; Mikolajick, Thomas
abstract

Novel hafnium oxide (HfO2)-based ferroelectrics reveal full scalability and complementary metal oxide semiconductor integratability compared to perovskite-based ferroelectrics that are currently used in nonvolatile ferroelectric random access memories (FeRAMs). Within the lifetime of the device, two main regimes of wake-up and fatigue can be identified. Up to now, the mechanisms behind these two device stages have not been revealed. Thus, the main scope of this study is an identification of the root cause for the increase of the remnant polarization during the wake-up phase and subsequent polarization degradation with further cycling. Combining the comprehensive ferroelectric switching current experiments, Preisach density analysis, and transmission electron microscopy (TEM) study with compact and Technology Computer Aided Design (TCAD) modeling, it has been found out that during the wake-up of the device no new defects are generated but the existing defects redistribute within the device. Furthermore, vacancy diffusion has been identified as the main cause for the phase transformation and consequent increase of the remnant polarization. Utilizing trap density spectroscopy for examining defect evolution with cycling of the device together with modeling of the degradation results in an understanding of the main mechanisms behind the evolution of the ferroelectric response.

2016 - Root cause of degradation in novel HfO2-based ferroelectric memories [Relazione in Atti di Convegno]
Pesic, Milan; Fengler, Franz P. G.; Slesazeck, Stefan; Schroeder, Uwe; Mikolajick, Thomas; Larcher, Luca; Padovani, Andrea
abstract

HfO2-based ferroelectrics reveal full scalability and CMOS integratability compared to perovskite-based ferroelectrics that are currently used in non-volatile ferroelectric random access memories (FeRAMs). Up to now, the mechanisms responsible for the decrease of the memory window have not been revealed. Thus, the main scope of this study is an identification of the root causes for the endurance degradation. Utilizing trap density spectroscopy for examining defect evolution with cycling of the device studied together with modeling of the degradation resulted in an understanding of the main mechanisms responsible for degradation of the ferroelectric behavior.

2016 - Single vacancy defect spectroscopy on HfO2 using random telegraph noise signals from scanning tunneling microscopy [Articolo su rivista]
Thamankar, R.; Raghavan, N.; Molina, J.; Puglisi, Francesco Maria; O'Shea, S. J.; Shubhakar, K.; Larcher, Luca; Pavan, Paolo; Padovani, Andrea; Pey, K. L.
abstract

Random telegraph noise (RTN) measurements are typically carried out at the device level using standard probe station based electrical characterization setup, where the measured current represents a cumulative effect of the simultaneous response of electron capture/emission events at multiple oxygen vacancy defect (trap) sites. To better characterize the individual defects in the high-j dielectric thin film, we propose and demonstrate here the measurement and analysis of RTN at the nanoscale using a room temperature scanning tunneling microscope setup, with an effective area of interaction of the probe tip that is as small as 10 nm in diameter. Two-level and multi-level RTN signals due to single and multiple defect locations (possibly dispersed in space and energy) are observed on 4 nm HfO2 thin films deposited on n-Si (100) substrate. The RTN signals are statis- tically analyzed using the Factorial Hidden Markov Model technique to decode the noise contribu- tion of more than one defect (if any) and estimate the statistical parameters of each RTN signal (i.e., amplitude of fluctuation, capture and emission time constants). Observation of RTN at the nanoscale presents a new opportunity for studies on defect chemistry, single-defect kinetics and their stochastics in thin film dielectric materials. This method allows us to characterize the fast traps with time constants ranging in the millisecond to tens of seconds range.

2015 - A Complete Statistical Investigation of RTN in HfO₂-Based RRAM in High Resistive State [Articolo su rivista]
Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance.

2015 - A microscopic physical description of RTN current fluctuations in HfOx RRAM [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Vandelli, Luca; Padovani, Andrea; Bertocchi, Matteo; Larcher, Luca
abstract

In this work we explore the microscopic mechanisms responsible for Random Telegraph Noise (RTN) current fluctuations in HfOx Resistive Random Access Memory (RRAM) devices. The statistical properties of the RTN current fluctuations are analyzed in a variety of reading conditions by exploiting the Factorial Hidden Markov Model (FHMM) to decompose the complex RTN traces in a superimposition of two-level fluctuations. We investigate the physical mechanisms that could be responsible for the RTN current fluctuations by considering two options that are the Coulomb blockade effect and the metastable-to-stable transition of defect assisting the Trap- Assisted-Tunneling (TAT) charge transport. Physics-based simulations show that both options allow reproducing the RTN current fluctuations. The electron TAT via oxygen vacancy defects, responsible for the current in High Resistive State (HRS), is significantly altered by the electric field caused by electron trapping at defects (i.e. neutral interstitial oxygen), not directly involved in charge transport. Similarly, the transition of oxygen vacancies into a stable-slow defect configuration (still unidentified in HfOx) can temporarily switch off the current, thus explaining the RTN.

2015 - Characterization of anomalous Random Telegraph Noise in Resistive Random Access Memory [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper we explore the features of complex anomalous Random Telegraph Noise (aRTN) in TiN/Ti/HfO2/TiN Resistive Random Access Memory (RRAM) devices. Careful design of experiment, dedicated characterization techniques, and physics-based simulations are exploited to gain insights into the physics of this phenomenon. The RTN parameters (amplitude of the current fluctuations, capture and emission times) observed in the experiments are analyzed in a variety of operating conditions. Anomalous behaviors are examined and their statistical characteristics are analyzed. Physics-based simulations taking into account both the Coulomb interactions among different defects in the device and the possibility for defects to show metastable states are exploited to suggest a possible origin of the aRTN. Results highlight the importance of the electrostatic interactions among individual defects and the trapped charge.

2015 - Cross-correlation of electrical measurements via physics-based device simulations: Linking electrical and structural characteristics [Relazione in Atti di Convegno]
Padovani, A.; Larcher, L.; Vandelli, L.; Bertocchi, M.; Cavicchioli, R.; Veksler, D.; Bersuker, G.
abstract

We present a comprehensive simulation framework to interpret electrical characteristics (I-V, C-V, G-V, Charge-Pumping, BTl, CVS, RVS, ...) commonly used for material characterization and reliability analysis of gate dielectric stacks in modern semiconductor devices. By accounting for the physical processes controlling charge transport through the dielectric (e.g. carrier trapping/de-trapping at the defect sites, defect generation, etc.), which is modeled using a novel approach based of material characteristics, the simulations provide a unique link between the electrical measurements data and specific atomic defects in the dielectric stack. Within this methodology, the software allows an accurate defect spectroscopy by cross-correlating measurements of pre-stress electrical parameters (IV, CV, BTl). These data are then used to project the stack reliability through the simulations of stress-induced leakage current (SILC) and time-dependent dielectric degradation trends, demonstrating the tool capabilities as a technology characterization/optimization benchmark.

2015 - Microscopic Modeling of HfOₓ RRAM Operations: From Forming to Switching [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; Pirrotta, Onofrio; Vandelli, Luca; Bersuker, Gennadi
abstract

We propose a model describing the operations of hafnium oxide-based resistive random access memory (RRAM) devices at the microscopic level. Charge carrier and ion transport are self-consistently described starting from the leakage current in pristine HfO₂. Material structural modifications occurring during the RRAM operations, such as conductive filament (CF) creation and disruption, are accounted for. The model describes the complex processes leading to a formation of the CF and its dependence on both electrical conditions (e.g., current compliance, voltage stress, and temperature) and device characteristics (e.g., electrodes material and dielectric thickness).

2015 - Statistical analysis of random telegraph noise in HfO2-based RRAM devices in LRS [Articolo su rivista]
Puglisi, Francesco Maria; Pavan, Paolo; Larcher, Luca; Padovani, Andrea
abstract

In this work, we present a thorough statistical characterization of Random Telegraph Noise (RTN) in HfO2-based Resistive Random Access Memory (RRAM) cells in Low Resistive State (LRS). Devices are tested under a variety of operational conditions. A Factorial Hidden Markov Model (FHMM) analysis is exploited to extrapolate the properties of the traps causing multi-level RTN in LRS. The trapping and de-trapping of charge carriers into/out of defects located in the proximity of the conductive filament results in a shielding effect on a portion of the conductive filament, leading to the observed RTN current fluctuations. It is found that both oxygen vacancies and oxygen ions defects may be responsible for the observed RTN. The variations of the current observed at subsequent set/reset cycles are instead attributed to the stochastic variations in the filament due to oxidation/reduction processes during reset and set operations, respectively.

2014 - A Charge-Trapping Model for the Fast Component of Positive Bias Temperature Instability (PBTI) in High-k Gate-Stacks [Articolo su rivista]
Vandelli, Luca; Larcher, Luca; Veksler, Dmitry; Padovani, Andrea; Bersuker, Gennadi; Matthews, Kenneth
abstract

We propose a physical model for the fast component (<1 s) of the positive bias temperature instability (PBTI) process in SiOx/HfO2 gate-stacks. The model is based on the electron–phonon interaction governing the trapping/emission of injected electrons at the preexisting defects in the dielectric stack. The model successfully reproduces the experimental time dependences of the VTH shift on both stress voltage and temperature. Simulations allow the extraction of the physical characteristics of the defects contributing to PBTI, which are found to match those assisting the leakage current in these stacks (i.e., oxygen vacancies).

2014 - A Compact Model of Program Window in HfOx RRAM Devices for Conductive Filament Characteristics Analysis [Articolo su rivista]
Larcher, Luca; Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Vandelli, Luca; Bersuker, Gennadi
abstract

This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices.

2014 - A study on HfO2 RRAM in HRS based on I–V and RTN analysis [Articolo su rivista]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca
abstract

This paper presents a statistical characterization of random telegraph noise (RTN) in hafnium-oxide based resistive random access memories (RRAMs) in high resistive state (HRS). Complex RTN signals are analyzed exploiting a Factorial Hidden Markov Model (FHMM) approach, which allows to derive the statistical properties of the RTN signals, directly related to the physical properties of the traps responsible for the multi-level RTN measured in these devices. Noise characteristics in different reset conditions are explored through consecutive switching cycles. Noise spectral analysis is also performed to fully support the investigation. An RRAM compact model is also exploited to estimate the physical properties of the conductive filament and of the dielectric barrier from simple I–V data. These tools are combined together to prove the existence of a direct statistical relation between the reset conditions, the volume of the dielectric barrier created during the reset operation and the average number of active traps contributing to the RTN.

2014 - Analysis of Correlated Gate and Drain Random Telegraph Noise in Post-Soft Breakdown TiN/HfLaO/SiOx nMOSFETs [Articolo su rivista]
W. H., Liu; Padovani, Andrea; Larcher, Luca; N., Raghavan; K. L., Pey
abstract

We investigate correlated gate (IG) and drain (ID) random telegraph noise phenomena observed in post breakdown regime on nMOSFET TiN/HfLaO/SiOx gate stacks. We observe two different IG-ID correlation patterns (i.e. of the same and opposite polarities) that we attributed to charge trapping into oxygen vacancy traps of different kinds located in the SiOx close to the Si/SiOx interface. Results reported in this letter provide useful information for improving the understanding of IG/ID RTN phenomena and its impact on the reliability of post-SBD nanometer MOSFETs.

2014 - Analysis of RTN and cycling variability in HfO2 RRAM devices in LRS [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Larcher, Luca; Padovani, Andrea
abstract

In this work, we present a thorough statistical characterization of cycling variability and Random Telegraph Noise (RTN) in HfO2-based Resistive Random Access Memory (RRAM) cells in Low Resistive State (LRS). Devices are tested under a variety of operational conditions. A Factorial Hidden Markov Model (FHMM) analysis is exploited to extrapolate the properties of the traps causing multi-level RTN in LRS. The trapping and de-trapping of charge carriers into/out of defects located in the proximity of the conductive filament results in a shielding effect on a portion of the conductive filament, leading to the observed RTN current fluctuations. The variations of the current observed at subsequent set/reset cycles are instead attributed to the stochastic variations in the filament due to oxidation/reduction processes during reset and set operations, respectively. The statistical characterization of RTN and cycling variability does not show correlation between these phenomena.

2014 - Defect density evaluation in a high-k MOSFET gate stack combining experimental and modeling methods [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Veksler, D.; Matthews, K.; Bersuker, G.; Larcher, Luca; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo
abstract

We report on a methodology to assist fabrication process development using a case study of high thermal budget (HTB) and low thermal budget (LTB) fabrication flows for high- k/metal gate stacks in n-MOSFETs. This methodology is supported by simulations that self-consistently extract defect characteristics by simultaneously considering a set of electrical measurement data, specifically stress-induced leakage current (SILC), threshold voltage shift (PBTI), and multi-frequency charge-pumping (MFCP). The contributions of pre-existing and stress-induced defects in SiO2/HfO2 gate stacks on device performance are examined. Information on defect distributions, extracted in the as-fabricated and post-stress HTB and LTB devices, allow understanding their dependence on the fabrication process, which can provide guidelines for the process optimization.

2014 - Dielectric morphology and RRAM resistive switching characteristics [Relazione in Atti di Convegno]
Bersuker, G.; Butcher, B.; Gilmer, D. C.; Larcher, Luca; Padovani, A; Geer, R.; Kirsch, P. D.
abstract

The connection between the bi-polar hafnia-based resistive-RAM (RRAM) operational characteristics and dielectric structural properties is considered. Specifically, the atomic-level description of RRAM, which operations involve the repeatable rupture/recreation of a localized conductive path, reveals that its performance is determined by the outcome of the initial forming process defining the structural characteristics of the conductive filament and distribution of the oxygen ions released from the filament region. The post-forming ions spatial distribution in the cell is found to be linked to a degree of dielectric oxygen deficiency, which may either assist or suppress the resistive switching processes.

2014 - Instability of HfO2 RRAM devices: Comparing RTN and cycling variability [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Larcher, Luca; Pavan, Paolo; Padovani, Andrea; Bersuker, G.
abstract

In this study, we present an extensive statistical characterization of the cycling variability and Random Telegraph Noise (RTN) in the HfO2-based Resistive Random Access Memories (RRAM) cells. Devices with different dielectric stacks are tested under a variety of read (sampling times and read voltage magnitudes) and operational (reset voltages) conditions. A Factorial Hidden Markov Model (FHMM) analysis is employed to reveal the properties of the traps causing multi-level RTN in High Resistive State (HRS), while the I-V data are analyzed through the developed compact model to investigate cycling variability. The activation and deactivation of traps assisting the charge transport through a dielectric barrier in HRS is found to be responsible for the observed RTN while the read current variations can be attributed to the stochastic nature of the filament oxidation process during reset, also leading to a variable number of traps formed in the barrier after each switching cycle. The statistical characterization of RTN and cycling variability, which demonstrates the uncorrelated nature of these phenomena, provides guidelines for scaling and optimization of RRAM device operations and reliability.

2014 - Multi-scale modeling of oxygen vacancies assisted charge transport in sub-stoichiometric TiOx for RRAM application [Relazione in Atti di Convegno]
Pirrotta, Onofrio; Padovani, Andrea; Larcher, Luca; L., Zhao; B., Magyari Köpe; Y., Nishi
abstract

In this work we investigate the charge transport in sub-stoichiometric TiOx for RRAM applications. We explored the atomic defect configurations actively assisting the charge transport in sub-stoichiometric TiOx through a multi-scale approach. We combined density-functional-theory-based non-equilibrium Green's function approach (DFT-NEGF) with physical-based trap assisted tunneling (TAT) modeling to identify the defects dominating the current conduction mechanism and the physical parameters of the defects responsible for the trap-assisted tunneling (TAT). The values of the thermal ionization energy ET and relaxation energy EREL extracted are 0.35-0.4eV and 0.7eV, respectively.

2014 - Progresses in Modeling HfOx RRAM Operations and Variability [Relazione in Atti di Convegno]
Larcher, Luca; Pirrotta, Onofrio; Puglisi, Francesco Maria; Padovani, Andrea; Pavan, Paolo; Vandelli, Luca
abstract

This paper reports on recent progresses in modeling bi-polar RRAM devices based on hafnium oxide. The unique modeling environment adopted for the simulation of device operations accounts self-consistently for the charge and ion transport, and the structural device modification occurring during forming and set/reset operations. Reliability mechanisms as well as the major sources of devices variability are included thanks to a multi-scale approach that connects the electrical device performance to the atomic-level material properties. The modeling methodology can be successfully applied to both improve device performances and fabrication process of state-of-the-art RRAM devices, and devise device solutions for future 3D RRAM architectures.

2013 - A Compact Model of Hafnium-Oxide-Based Resistive Random Access Memory [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca
abstract

In this paper, a compact model of hafnium-oxide-based resistive random access memory (RRAM) cell is developed. The proposed model includes the effect of the temperature and cycle-to-cycle stochastic variations affecting the device operations. Simple I-V measurements are used to extract the model parameters. The model accurately reproduces the I-V curves of the switching cycles in different operating conditions.

2013 - A simulation framework for modeling charge transport and degradation in high-k stacks [Articolo su rivista]
Larcher, Luca; Padovani, Andrea; Vandelli, Luca
abstract

In this paper we present a comprehensive physical model that describes charge transport and degradation phenomena in high-k stacks. The physical mechanisms are modeled using a novel material-related approach that includes in a self-consistent fashion the charge transport (dominated by defect-assisted contribution), power dissipation and temperature increase, defect generation, and ion and vacancy diffusion and recombination. The physical properties of defects, which play a crucial role in determining the electrical behavior of the high-k stacks, depend on their atomistic configurations, as calculated using ab-initio methods. This simulation framework represents a powerful tool to interpret electrical characterization measurements. In addition, it can be used to optimize logic and memory device stacks thanks to its predictive statistical capabilities that allow reproducing gate current, threshold voltage increase and time to breakdown (TDDB) statistics. Simulation results performed using this simulation package are shown to reproduce accurately leakage current, Stress-Induced Leakage Current (SILC), threshold voltage shift observed during Positive Bias Temperature Instability (PBTI) stress, TDDB in various dielectric stacks.

2013 - An Empirical Model for RRAM Resistance in Low- and High-Resistance State [Articolo su rivista]
Puglisi, Francesco Maria; Larcher, Luca; G., Bersuker; Padovani, Andrea; Pavan, Paolo
abstract

We present a simple empirical expression describing hafnium-based RRAM resistance at different reset voltages and current compliances. The model that we propose describes filament resistance measured at low (∼0.1 V) reading voltage in both low-resistance state (LRS) and high-resistance state (HRS). The proposed description confirms that conduction in LRS is ohmic (after forming with a sufficiently high current compliance) and is consistent with the earlier description of HRS resistance as controlled by a trap-assisted electron transfer via traps in the oxidized portion of the filament. The length of the nonohmic part of the filament is found to be directly proportional to reset voltage. Moreover, low-frequency noise measurements at different reset voltages evidence a tradeoff between HRS resistance and noise in reading conditions.

2013 - Charge Transport and Degradation in HfO2 and HfOx Dielectrics [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; Gennadi, Bersuker; Pavan, Paolo
abstract

We combine experiments and simulations to investigate leakage current and breakdown (BD) in stoichiometric and sub-stoichiometric hafnium oxides. Using charge-transport simulations based on phonon-assisted carrier tunneling between trap sites, we demonstrate that higher currents generally observed in HfOx are due to a higher density of the as-grown oxygen vacancy defects assisting the charge transport. Reduction of the dielectric breakdown field (EBD) in HfOx is explained by the lower zero-field activation energy (EA,G) of the defect generation process, as extracted from time-dependent dielectric breakdown experiments.

2013 - Compact modeling of TANOS program/erase operations for SPICE-like circuit simulations [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

We present an analytical model of TANOS program/erase transients that can be used to implement a compact SPICE-like model of these memory devices. Simulation results obtained from a physics-based TANOS model are used to derive simple analytical formulas relating the program/erase currents and the centroid of the trapped charge distribution to operating conditions and stack composition. The model allows reproducing with a good agreement the experimental program/erase transients, thus providing a valuable tool for IC designers to optimize TANOS memory circuits, especially in the framework of multi-level applications.

2013 - Connecting RRAM Performance to the Properties of the Hafnia-based Dielectrics [Relazione in Atti di Convegno]
G., Bersuker; B., Butcher; D., Gilmer; P., Kirsch; Larcher, Luca; Padovani, Andrea
abstract

The connection between the resistive-RAM (RRAM) operational-mechanism, performance, and utilized-dielectric properties is described. Specifically, the atomic-level description of bi-polar hafnia-based RRAM, which operations involve the repeatable rupture/recreation of a localized conductive path, reveals that its performance is determined by the outcome of the initial forming process; defining the structural characteristics of the conductive filament and distribution of the oxygen ions released from the filament region. The ion distribution, in turn, is found to be linked to the level of dielectric oxygen deficiency, which may either assist or suppress the resistive switching process. With this improved understanding of the connection between RRAM performance and materials properties the optimization of RRAM devices may be more readily achieved.

2013 - Connecting the physical and electrical properties of Hafnia-based RRAM [Relazione in Atti di Convegno]
B., Butcher; G., Bersuker; D., Gilmer; P., Kirsch; Larcher, Luca; Padovani, Andrea; Vandelli, Luca; R., Geer; P. D., Kirsch
abstract

Simulations of the dynamic physical processes involved in HfO2-based resistive-memory-operations are used to identify the dielectric structural properties responsible for device performance, while revealing that repeatable switching and higher HRS resistances are enabled by the oxide substoichiometric composition. These simulations support a conductive-filament-formation physical model which is resulted from metal-oxygen bond breakage and subsequent oxygen ion out-diffusion, thus leaving behind an oxygen vacancy rich region. The subsequent reset process is also shown to be controlled by re-oxidation of the filament tip.

2013 - Identifying the First Layer to Fail in Dual Layer SiOx/HfSiON Gate Dielectric Stacks [Articolo su rivista]
Padovani, Andrea; Nagarajan, Raghavan; Larcher, Luca; Kin Leong, Pey
abstract

We use the thermochemical model of bond breakage to investigate the degradation occurring in dual layer SiOx/HfSiON gate dielectric stacks during low compliance soft breakdown experiments, with the ultimate goal of identifying the first layer that degrades. Time dependent dielectric breakdown (TDDB) experiments reveal that the degradation of conventional SiON and SiOx/HfSiON dielectric stacks have the same kinetics, i.e., activation energy and field acceleration factor. This finding, supported by physics-based breakdown simulations, indicates that the degradation in SiOx/HFSiON stacks is governed by the defect generation in the silicon oxide interfacial layer, which is the first that degrades in the multi-layer stack.

2013 - Investigation of the role of electrodes on the retention performance of HfOx based RRAM cells by experiments, atomistic simulations and device physical modeling [Relazione in Atti di Convegno]
B., Traore; K. H., Xue; E., Vianello; G., Molas; Padovani, Andrea; Pirrotta, Onofrio; Larcher, Luca; P., Blaise; L., Fonseca; B., De Salvo; Y., Nishi
abstract

In this work we investigate in detail the effects of metal electrodes on the retention performances of HfOx RRAM devices. Motivated by our experimental data, we employ physics-based RRAM modeling and first-principles calculations to show that during the ON-state the concentration of oxygen interstitial (Oi) ions in the oxide depends significantly on the metal electrodes, being much larger for RRAM devices with Pt electrodes compared with Ti. The lower Oi concentration in HfOx with Ti electrodes, known as a strong oxygen getter material, results in improved retention and thermal stability. The presence of oxygen deficient conductive filaments explains the data.

2013 - Leakage Current - Forming Voltage Relation and Oxygen Gettering in HfOx RRAM Devices [Articolo su rivista]
K. G., Young Fisher; G., Bersuker; B., Butcher; Padovani, Andrea; Larcher, Luca; D., Veksler; D. C., Gilmer
abstract

We observe a trend between initial leakage currents in polycrystalline HfOx resisitive random access memory (RRAM) cells (before forming) and the forming voltages. This trend points to the dominant role played by conduction paths located at grain boundaries, which is promoted by the oxygen deficiency in ${rm HfO}_{rm x}$. One of these paths is then converted into the conductive filament responsible for nonvolatile resistance switching. In addition, we find that by engineering the RRAM stack, the forming voltage can be tuned-up to meet specific RRAM requirements, such as lower power and forming-less operations.

2013 - Leakage current through the poly-crystalline HfO2: trap densities at grains and grain boundaries [Articolo su rivista]
Pirrotta, Onofrio; Larcher, Luca; M., Lanza; Padovani, Andrea; M., Porti; Nafría, M. o.; G., Bersuker
abstract

We investigate the role of grains and grain boundaries (GBs) in the electron transport through poly-crystalline HfO2 by means of conductive atomic force microscopy (CAFM) measurements and trap-assisted tunneling simulations. CAFM experiments demonstrate that the leakage current through a thin dielectric film preferentially flows via the GBs. The current I-V characteristics measured on both types of sites, grains, and GBs are successfully simulated by utilizing the multiphonon trap-assisted tunneling model, which accounts for the inelastic charge transport via the electron traps. The extracted density of electrically active traps, whose energy parameters match those of the positively charged oxygen vacancies in hafnia, is ∼3 × 1019 cm−3 at the grains, whereas a much higher value of (0.9÷2.1) × 1021 cm−3 is required to reproduce the leakage current through the GBs.

2013 - Microscopic Modeling of Electrical Stress -Induced Breakdown in Poly-Crystalline Hafnium Oxide Dielectrics [Articolo su rivista]
Vandelli, Luca; Padovani, Andrea; Larcher, Luca; G., Bersuker
abstract

We present a quantitative physical model describing degradation of poly-crystalline HfO2 dielectrics subjected to electrical stress culminating in the dielectric breakdown (BD). The model accounts for the morphology of the hafnium oxide film and considers the interaction of the injected electrons with the atomic defects supporting the charge transport to calculate the 3D power dissipation and temperature maps across the dielectric. This temperature map, along with that of the electric field, is used to self-consistently calculate the stress-induced defect generation rates in the dielectric during stress. The model quantitatively reproduces the evolution of the currents measured on HfO2 MIM capacitors during constant voltage stress, up to the onset of BD, and the dependencies of the time-dependent dielectric breakdown (TDDB) distributions on stress temperature and voltage. It represents a powerful tool for statistical reliability predictions that can be extended to other high-k materials, multilayer stacks and resistive RAM devices based on transition metal oxides.

2013 - Modeling the Effects of Different Forming Conditions on RRAM Conductive Filament Stability [Relazione in Atti di Convegno]
B., Butcher; G., Bersuker; Vandelli, Luca; Padovani, Andrea; Larcher, Luca; A., Kalantarian; R., Geer; D. C., Gilmer
abstract

In order to identify the factors controlling the filament characteristics, we perform physics-based simulations of the inherently stochastic and difficult-to-control forming process using a statistical Monte-Carlo method to model the Hf-O bond-breakage, oxygen ion diffusion and vacancy-oxygen recombination. Simulation results well reproduce the experimental trends observed for the conductivity of the post-forming low resistance state under different forming conditions. It is shown that the distribution of the oxygen ions in the surrounding oxide during forming as well as local filament temperature and electrical field all affect the filament stability.

2013 - Perimeter and area current components in HfO2 and HfO2-x metal-insulator-metal capacitors [Articolo su rivista]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca
abstract

In this paper, the authors present an experimental analysis on current conduction mechanisms in high-k oxides, where two metal–insulator–metal structures with different insulators (HfO2 and HfO2-x) are considered. Current density measurements indicate the existence of a perimeter-related component in the current, sizeable in HfO2, and negligible in HfO2-x samples, which have to be taken into account for a correct analysis of the device behavior and cannot be based only on the area scaling rules. For oxide breakdown, for example, a significant contribution of the perimeter-related current component results in conservative extrapolations of breakdown voltages for scaled devices.

2013 - RTS Noise Characterization of HfOx RRAM in High Resistive State [Articolo su rivista]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca; G., Bersuker
abstract

In this paper we analyze Random Telegraph Signal (RTS) noise cand Power Spectral Density (PSD) in hafnium-based RRAMs. RTS measured in HRS exhibits fast and slow multilevel switching events. RTS characteristics are examined through novel color-coded time-lag plots and Hidden Markov Model (HMM) time-series analyses. Results are validated by comparing simulated and experimental PSD. Noise is examined at different reset conditions to provide an insight into the conduction mechanisms in HRS. Higher reset voltages are found to result in greater RTS complexity due to a larger number of active traps as confirmed by PSD.

2013 - Random Telegraph Noise analysis to investigate the properties of active traps of HfO2-Based RRAM in HRS [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca
abstract

This paper presents statistical characterization of Random Telegraph Noise (RTN) in hafnium-oxide-based Resistive Random Access Memories (RRAMs) in High Resistive State (HRS). Complex RTN signals are analyzed exploiting a Factorial Hidden Markov Model (FHMM) approach, allowing to derive the statistical properties of traps responsible of the multi-level RTN measured in these devices. Noise characteristics in different reset conditions are explored to prove the existence of a direct relation between the reset voltage, the volume of the dielectric barrier created during the reset operation and the number of active traps contributing to the RTN.

2013 - Random telegraph noise (RTN) in scaled RRAM devices [Poster]
D., Veksler; G., Bersuker; Vandelli, Luca; Padovani, Andrea; Larcher, Luca; A., Muraviev; B., Chakrabarti; E., Vogel; D. C., Gilmer; P. D., Kirsch
abstract

The random telegraph noise (RTN) related read instability in resistive random access memory (RRAM) is evaluated by employing the RTN peak-to-peak (P-p) amplitude as a figure of merit (FoM). Variation of the FoM value over multiple set/reset cycles is found to follow the log-normal distribution. In HRS, P-p decreases with the reduction of the read current, which allows scaling of the RRAM operating current. The RTN effect is attributed to the mechanism of activation/deactivation of the electron traps in (in HRS) or near (in LRS) the filament that affects the current through the RRAM device.

2013 - Resilience of Ultra-Thin Oxynitride Films to Percolative Wear-Out and Reliability Implications for High-k Stacks at Low Voltage Stress [Articolo su rivista]
N., Raghavan; Padovani, Andrea; X., Li; X., Wu; V. L., Lo; M., Bosman; Larcher, Luca; K. L., Pey
abstract

Localized progressive wear-out and degradation of ultra-thin dielectrics around the oxygen vacancy percolation path formed during accelerated time dependent dielectric breakdown (TDDB) tests is a well-known phenomenon documented for silicon oxynitride (SiON) based gate stacks in metal oxide semiconductor field effect transistors (MOSFET). This progressive or post breakdown stage involves an initial phase characterized by “digital” random telegraph noise (RTN) fluctuations followed by the wear-out of the percolation path, which results in an “analog” increase of the leakage current towards the compliance, culminating in a thermal runaway and hard breakdown (HBD). The relative contribution of the digital and analog phases of degradation at very low voltage stress in ultra-thin SiON (16Ǻ) is yet to be fully investigated, which represents the core of this study. We investigate the wear-out process by combining electrical and physical analysis evidences with modeling and simulation results using Kinetic Monte Carlo (KMC) defect generation and multi-phonon trap assisted tunneling (PTAT) models. We show that the transition from the digital to the analog regime is governed by a critical voltage (VCRIT), which determines the reliability margin in the post breakdown phase. Our results have a significant impact on the post-breakdown operational reliability of SiON and advanced high-κ – SiOx interfacial layer (HK-IL) gate stacks, wherein the SiOx layer seems to be the weakest link for percolation event.

2013 - Temperature impact (up to 200 °C) on performance and reliability of HfO2-based RRAMs [Relazione in Atti di Convegno]
T., Cabout; L., Perniola; V., Jousseaume; H., Grampeix; J. F., Nodin; A., Toffoli; E., Jalaguier; E., Vianello; G., Molas; G., Reimbold; B., De Salvo; Pirrotta, Onofrio; Padovani, Andrea; Larcher, Luca; T., Diokh; P., Candelier; M., Guillermet; M., Bocquet; C., Muller
abstract

This paper provides an overview of the temperature impact (up to 200 °C) on the electrical behavior of oxide-based RRAM, during forming, low-field resistance reading, SET/RESET, disturb, data retention and endurance. . HfO2-RRAM devices (in a 1T1R configuration) integrated in an advanced 65 nm technology are studied for this aim. We show that forming operation is strongly activated in temperature (i.e. -0.5 V per hundred Celsius degree), being much less for SET and RESET voltages (i.e. < -0.05 V per hundred Celsius degree); disturb of HRS at fixed voltage showed to be independent of temperature; endurance up to 3.106 cycles, with optimized set of stress parameters showed no significant variation; data retention at 150 °C up to 68 days showed stable programming window, after different initial programming algorithms.

2013 - The "Buffering" Role of High-k in Post Breakdown Degradation Immunity of Advanced Dual Layer Dielectric Gate Stacks [Relazione in Atti di Convegno]
N., Raghavan; Padovani, Andrea; X., Wu; K., Shubhakar; M., Bosman; Larcher, Luca; K. L., Pey
abstract

Post breakdown (BD) reliability is an important area of study in ultra-thin gate dielectrics as it has significant implications on the performance degradation, lifetime, reliability margin and power dissipation of advanced sub-22 nm transistors and circuits. A prolonged phase of post-BD can ensure we can live with the circuit with moderate performance and error-free operation, even if the soft breakdown (SBD) events occur early. While analysis of post-BD is simple and straightforward for single layer SiO2 / SiON stacks, the number of possible scenarios of post-BD increases when analyzing high-κ – interfacial layer (HK-IL) based technology. This is because the sequence of BD (whether HK or IL fails first followed by the other one) and the competition between multiple SBD in one of these layers, dilative wear-out of a single SBD spot and the possibility of a successive localized BD above / below the HK/IL BD percolation spot (with or without metal filamentation) are all possible phenomena that can be classified as post-BD. The likelihood of occurrence of these various possibilities will determine the immunity of the stack to post-BD degradation. We will investigate each of these scenarios in detail in this work in order to provide a comprehensive assessment of post-BD reliability of state-of-the-art technology. Our analysis on a HK:IL = 25:12Ǻ stack supported by electrical, physical and modeling results provides clear evidence that circuit failure at operating conditions can only be due to multiple SBD events within the IL layer and that the HK is very robust and resilient to breakdown.

2012 - A study of the leakage current in TiN/HfO2/TiN capacitors [Articolo su rivista]
S., Cimino; Padovani, Andrea; Larcher, Luca; V. V., Afanas’Ev; H. J., Hwang; Y. G., Lee; M., Jurczac; D., Wouters; B. H., Lee; H., Hwang; L., Pantisano
abstract

Physical and electrical characteristics of Metal–Insulator–Metal TiN/HfO2/TiN capacitors have been investigated. A detailed study using internal photoemission and trap assisted transport simulation enabled the extraction of relevant important parameters like barrier height (2.5 eV) for both injecting interfaces, optical energy gap (5.6 eV), as well as trap density and energy position within the bandgap (NT = 3E19 cm-3; rT = 1E14 cm2; ET = 2.0–2.6 eV below the bottom of the HfO2 conduction band). The extracted parameters surprisingly showed striking similarities with HfO2 deposited on a Si surface, i.e., in MOSFET process flow. Additionally, Constant Voltage Stress showed a leakage current increase, preferentially at low voltage. This can be explained by preexisting defect precursors (likely related to oxygen vacancies) or by involvement of hydrogen in creating defects as observed on thermal SiO2 layers.

2012 - Controlling Uniformity of RRAM Characteristics via the Forming Process [Relazione in Atti di Convegno]
A., Kalantarian; G., Bersuker; D. C., Gilmer; D., Veksler; B., Butcher; Padovani, Andrea; Pirrotta, Onofrio; Larcher, Luca; P., Kirsch; Y., Nishi
abstract

The proposed constant voltage forming (CVF) is shown to increase the resistances of the low resistance and high resistance states while reducing their variability. By forcing the forming in all devices to occur at the same predefined voltage,the CVF method eliminates a major cause of the device-to-device variation associated with the randomness of the forming voltage values. Moreover,both experiments and simulations show that CVF at lower voltages suppresses the parasitic overshoot current,resulting in a more controlled and smaller filament cross-section and lower operation currents.

2012 - Controlling uniformity of RRAM characteristics through the forming process [Relazione in Atti di Convegno]
Kalantarian, A.; Bersuker, G.; Gilmer, D. C.; Veksler, D.; Butcher, B.; Padovani, A.; Pirrotta, O.; Larcher, L.; Geer, R.; Nishi, Y.; Kirsch, P.
abstract

The proposed constant voltage forming (CVF) is shown to increase the resistances of the low resistance and high resistance states while reducing their variability. By forcing the forming in all devices to occur at the same predefined voltage, the CVF method eliminates a major cause of the device-to-device variation associated with the randomness of the forming voltage values. Moreover, both experiments and simulations show that CVF at lower voltages suppresses the parasitic overshoot current, resulting in a more controlled and smaller filament cross-section and lower operation currents. © 2012 IEEE.

2012 - DENSITY INFLUENCE ON AMORPHOUS HFO2 STRUCTURE: A MOLECULAR DYNAMICS STUDY [Relazione in Atti di Convegno]
Broglia, Giulia; Montorsi, Monia; Larcher, Luca; Padovani, Andrea
abstract

In this scenario, the aim of this work is to analyse systematically the influence of the materialdensity on the structure of amorphous HfO2 (a-HfO2). We will focus on investigating theatomic structure in the short, medium and long range in order to understand which is the preferential atomic structure.The molecular dynamics technique has been chosen for this analysis because it permits to investigate accurately the short and medium structural order of this material.

2012 - Evidences for vertical charge dipole formation in charge-trapping memories and its impact on reliability [Articolo su rivista]
Padovani, Andrea; A., Arreghini; Vandelli, Luca; Larcher, Luca; G., Van den bosch; J., Van Houdt
abstract

We demonstrate the formation of a vertical charge dipole in the nitride layer of TaN/Al2O3/Si3N4/SiO2/Si memories and use dedicated experiments and device simulations to investigate its dependence on program and erase conditions. We show that the polarity of the dipole depends on the program/erase operation sequence and demonstrate that is at the origin of the charge losses observed during retention. This dipole severely affects the retention of mildly programmed and erased states, representing a serious reliability concern especially for multi-level applications.

2012 - Leakage current in HfO2 stacks: from physical to compact modeling [Relazione in Atti di Convegno]
Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper we discuss the physical mechanisms governing the charge transport inside hafnium based dielectric stack from a modeling perspective. We propose a detailed Monte-Carlo physical model, which describes the charge transport across high-k stacks through the multiphonon trap-assisted-tunneling theory. This model reproduces accurately the voltage and temperature dependencies of the leakage current across HfO2-based stacks. Starting from this physical description, we develop an analytical model for the TAT current across high-k stacks, which can be implemented into SPICE-like circuit simulators. Despite the simplifying approximations, this compact model reproduces accurately the measurements, thus representing an effective tool for the investigation of the TAT currents.

2012 - Microscopic understanding and modeling of HfO2 RRAM device physics [Relazione in Atti di Convegno]
Larcher, Luca; Padovani, Andrea; Pirrotta, Onofrio; Vandelli, Luca; G., Bersuker
abstract

In this paper we investigate the physical mechanisms governing operations in HfOx RRAM devices. Forming set and reset processes are studied using a model including power dissipation associated with the charge transport, and the corresponding temperature increase, which assists ion diffusion.

2012 - New Insights into SILC Monitoring During TDDB Stress [Relazione in Atti di Convegno]
C. D., Young; G., Bersuker; M., Jo; K., Matthews; J., Huang; S., Deora; K. W., Ang; T., Ngai; Padovani, Andrea; Larcher, Luca; Chris, Hobbs; P. D., Kirsch
abstract

The breakdown (TDDB/SILC) characteristics of nMOS transistors with hafnium-based gate dielectric stacks of various zirconium content were investigated. It is found that the gate stack composition affects the SILC-voltage dependency while the voltage value chosen for SILC monitoring impacts significantly the SILC-based lifetime projection. For the worst case lifetime evaluation, SILC should be monitored at its maximum value rather than at any pre-defined, fixed voltage.

2012 - New insights into SILC-based life time extraction [Relazione in Atti di Convegno]
Young, C. D.; Bersuker, G.; Jo, M.; Matthews, K.; Huang, J.; Deora, S.; Ang, K. W.; Ngai, T.; Hobbs, C.; Kirsch, P. D.; Padovani, A.; Larcher, Luca
abstract

The breakdown (TDDB/SILC) characteristics of nMOS transistors with hafnium-based gate dielectric stacks of various zirconium content were investigated. It is found that the gate stack composition affects the SILC-voltage dependency while the voltage value chosen for SILC monitoring impacts significantly the SILC-based lifetime projection. For the worst case lifetime evaluation, SILC should be monitored at its maximum value rather than at any pre-defined, fixed voltage

2012 - Random Telegraph Signal Noise Properties of HfOx RRAM in High Resistive States [Relazione in Atti di Convegno]
Puglisi, Francesco Maria; Pavan, Paolo; Padovani, Andrea; Larcher, Luca; G., Bersuker
abstract

In this paper we analyze Random Telegraph Signal (RTS) noise in hafnium-based RRAMs. RTS is measured in HRS, showing fast and slow multilevel switching events. RTS characteristics are examined through novel color-coded time-lag plots and Hidden Markov Model (HMM) time-series analyses. Noise is examined at different reset conditions to provide new insights on conduction mechanisms in HRS. Higher reset voltages result in an enhanced complexity in RTS due to a larger number of active traps

2012 - Understanding the Role of the Ti Metal Electrode on the Forming of HfO2-based RRAMs [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo; C., Cagli; B., de Salvo
abstract

In this paper we investigate in details the effects of the Ti metal electrode on the forming operation in HfO2 RRAM devices. Starting from electrical data and physico-chemical analysis, we use physics-based RRAM modeling to understand the physics governing the CF formation in RRAM stacks with Ti electrodes. Simulations show that the lower forming voltage typically observed in these devices is due to the Ti-induced formation of a sub-stoichiometric HfOx region in the resistive switching layer. The model allows extracting the characteristics of this sub-stoichiometric region that are crucial for developing future low-voltage RRAM devices.

2011 - A Comprehensive Understanding of the Erase of TANOS Memories Through Charge Separation Experiments and Simulations [Articolo su rivista]
Padovani, Andrea; A., Arreghini; Vandelli, Luca; Larcher, Luca; G., Van den Bosh; Pavan, Paolo; J., Van Houdt
abstract

We investigate and quantify the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations. Results demonstrate that electron emission via trap to-band tunneling dominates the first part of the erase operation, whereas hole injection prevails in the remaining part of the transient. In addition, we show that the efficiency of the erase operation is high and constant mainly because of the high energy offset between nitride and alumina valence bands. Our results clearly identify the physical mechanisms responsible for TANOS erase and allow deriving some important guidelines for the optimization of this operation.

2011 - A Physical model of the temperature dependence of the current through SiO2/HfO2 stacks [Articolo su rivista]
Vandelli, Luca; Padovani, Andrea; Larcher, Luca; R. G., Southwick III; W. B., Knowlton; G., Bersuker
abstract

In this paper, we investigate the characteristics of the defects responsible for the leakage current in the SiO2 and SiO2/HfO2 gate dielectric stacks in a wide temperature range (6 K–400 K). We simulated the temperature dependence of the I–V characteristics both at positive and negative gate voltages by applying the multiphonon trap-assisted tunneling model describing the charge transport through the dielectric. In the depletion/weak inversion regime, the current is limited by the supply of carriers available for tunneling. In strong inversion, the temperature dependence is governed by the charge transport mechanisms through the stacks; in particular, in SiO2/HfO2 dielectric stacks, the coupling of the injected carriers with the dielectric phonons at the trap sites is the dominant mechanism.Matching the simulation results to the measurement data allows extracting important trap parameters, e.g., the trap relaxation and ionization energies, which identify the atomic structure of the electrically active defects in the gate dielectric.

2011 - A Physics-Based Model of the Dielectric Breakdown in HfO2 for Statistical Reliability Prediction [Relazione in Atti di Convegno]
Vandelli, Luca; G., Bersuker; Padovani, Andrea; J. H., Yum; Larcher, Luca; Pavan, Paolo
abstract

We present a quantitative physical model describingthe current evolution due to the formation of a conductivefilament responsible for the HfO2 dielectric breakdown. Bylinking the microscopic properties of the stress-generatedelectrical defects to the local power dissipation and to thecorresponding temperature increase along the conductive paththe model reproduces the rapid current increase observed duringthe breakdown. The model successfully simulates theexperimental time-dependent dielectric breakdown distributionsmeasured in HfO2 MIM capacitors under constant voltage stress,thus providing a statistical reliability prediction capability, whichcan be extended to other high-k materials, multilayer stacks,resistive memories based on transition metal oxides, etc.

2011 - Charge transport in high-k stacks for charge-trapping memory applications: A modeling perspective (invited) [Articolo su rivista]
Larcher, Luca; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo
abstract

Charge trapping (CT) memories could be a promising technology option for further NAND Flash scaling. The assessment of the scalability limits and ultimate performances of this technology demands for the comprehensive understanding of the physical mechanisms governing device operation and reliability, which requires accurate physics-based models reproducing the electrical device characteristics. The basic features of the models presented in the literature for CT memory devices are reviewed, underlining theirsimilarities and differences, and highlighting their importance in order to achieve a comprehensive understanding of the physical mechanisms responsible for CT device operation and reliability. A physical model describing the charge transport in nitride and high-j stacks is also presented, which allows gaining further insights into reliability issues related to charge localization and high-j tunnel and blocking dielectrics, like the effects of the blocking alumina layer and the band-gap engineered tunnel dielectrics on the TANOS device retention.

2011 - Charge trapping in alumina and its impact on the operation of metal-alumina-nitride-oxide-silicon memories: experiments and simulations [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; DELLA MARCA, Vincenzo; Pavan, Paolo; H., Park; G., Bersuker
abstract

We investigate electron/hole trapping phenomena in alumina blocking oxide and their impact on the program/erase operations and retention of TANOS memory devices. For this purpose, we perform simulations using a physical model reproducing charge injection/trapping in TANOS devices, which is extended to account for the charge trapping phenomena in the blocking layer. We derive the electrical characteristics of both electron and hole traps in Al2O3 by reproducing the measured program, erase and retention transients. Our results show that the amount of electron charge trapped in the alumina during a program operation strongly depends on the stack composition and program voltages and can account for up to 25% of the total threshold voltage shift, whereas hole trapping during erase is negligible. Finally, we investigate the degradation of retention caused by the electron trapping in the alumina blocking layer, which is shown to result in accelerated charge loss.

2011 - Comprehensive physical modeling of forming and switching operations in HfO2 RRAM devices [Relazione in Atti di Convegno]
Vandelli, Luca; Padovani, Andrea; Larcher, Luca; G., Broglia; G., Ori; Montorsi, Monia; G., Bersuker; Pavan, Paolo
abstract

In this work we apply a physical model based on charge transport and molecular mechanics/dynamics simulations to investigate the physical mechanisms governing the RRAM forming and switching operations. The proposed model identifies the major driving forces controlling conductive filament (CF) formation and changes during RRAM switching, thus providing a tool for investigation and optimization of RRAM devices.

2011 - Connecting electrical and structural dielectric characteristics [Relazione in Atti di Convegno]
G., Bersuker; D., Veksler; C. D., Young; H. Park W., Taylor; P., Kirsch; R., Jammy; Morassi, Luca; Padovani, Andrea; Larcher, Luca
abstract

An attempt is made to correlate electrical measurement results to specific defects in the dielectric stacks of high-k/metal gate devices. Defect characteristics extracted from electrical data were compared to those obtained by ab initio calculations of the dielectric structures. It is demonstrated that oxygen vacancies in a variety of charge states and configurations in the interfacial SiO2 layer of the high-k gate stacks contribute to random telegraph noise signal, time-dependent dielectric breakdown, and the flatband voltage roll-off phenomenon.

2011 - Experimental and Theoretical Study of Electrode Effects in HfO2 based RRAM [Relazione in Atti di Convegno]
C., Cagli; J., Buckley; V., Jousseaume; A., Salaun; H., Grampeix; J. F., Nodin; H., Feldis; A., Persico; J., Cluzel; P., Lorenzi; L., Massari; R., Rao; F., Irrera; T., Cabout; F., Aussenac; C., Carabasse; M., Coue; P., Calka; E., Martinez; L., Perniola; P., Blaise; Z., Fang; Y. H., Yu; G., Ghibaudo; D., Deleruyelle; M., Bocquet; C., Muller; Padovani, Andrea; Pirrotta, Onofrio; Vandelli, Luca; Larcher, Luca; G., Reimbold; B., de Salvo
abstract

In this work, the impact of Ti electrodes on the electricalbehaviour of HfO2-based RRAM devices is conclusivelyclarified. To this aim, devices with Pt, TiN and Ti electrodeshave been fabricated. We first provide severalexperiments to clearly demonstrate that switching is driven bycreation-disruption of a conductive filament. Thus, the role ofTiN/Ti electrodes is explained and modeled based on thepresence of HfOx interfacial layer underneath the electrode. Inaddition, Ti is found responsible to activate bipolar switching.Moreover, it strongly reduces forming and switching voltageswith respect to Pt-Pt devices. Finally, it positively impacts onretention. To support and interpret our results we providephysico-chemical measurements, electrical characterization,ab-initio calculations and modeling.

2011 - Grain boundary-driven leakage path formation in HfO2 dielectrics [Articolo su rivista]
G., Bersuker; J., Yum; Vandelli, Luca; Padovani, Andrea; Larcher, Luca; V., Iglesias; M., Porti; M., Nafría; K., Mckenna; A., Shluger; P., Kirsch; R., Jammy
abstract

The evolution over time of the leakage current in HfO2-based MIM capacitors under continuous or periodic constant voltage stress (CVS) was studied for a range of stress voltages and temperatures. The data were analyzed based on the results of conductive atomic force microscopy (AFM) measurements demonstrating preferential current flow along grain boundaries (GBs) in the HfO2 dielectric and ab initio calculations, which show the formation of a conductive sub-band due to the precipitation of oxygen vacancies at the GBs. The simulations using the statistical multi-phonon trap-assisted tunneling (TAT) current description successfully reproduced the experimental leakage current stress time dependency by using the calculated energy characteristics of the O-vacancies. The proposed model suggests that the observed reversible increase in the stress current is caused by segregation of the oxygen vacancies at the GBs and their conversion to the TAT-active charge state caused by reversible electron trapping during CVS.

2011 - Interface-trap effects in inversion-type enhancement-mode InGaAs/ZrO2 n-channel MOSFETs [Articolo su rivista]
Morassi, Luca; Padovani, Andrea; Verzellesi, Giovanni; D., Veksler; I., Ok; G., Bersuker
abstract

Interface-trap effects are analyzed in inversion-type enhancement-mode In0.53Ga0.47As/ZrO2 and In0.53Ga0.47As/In0.2Ga0.8As/ZrO2 n-channel MOSFETs bycomparing the measurements and the numerical device simulationsof dc transfer characteristics. Device simulations can reproduce measured threshold voltages under the hypothesis thatinterface traps are donorlike throughout the InGaAs band gap,allowing for strong inversion operation regardless of the relativelyhigh interface-trap density. The effects induced by the donorlikeinterface traps in MOSFETs having a thin In0.2Ga0.8As cap layer interposed between gate dielectric and channel are qualitatively different from those observed in standard MOSFETs (without the cap). Increasing the donorlike trap density decreases the threshold voltage in capped devices, whereas it leaves it unchanged in uncapped ones. As a result, donorlike interface traps can explain the threshold-voltage difference observed in MOSFETs with and without the cap.

2011 - Low Power RRAM with Improved HRS/LRS Uniformity through Efficient Filament Control Using CVS Forming [Relazione in Atti di Convegno]
A., Kalantarian; G., Bersuker; D. C., Gilmer; B., Butcher; Padovani, Andrea; Vandelli, Luca; Larcher, Luca; R., Geer; Y., Nishi; P., Kirsch
abstract

Resistance change memory (RRAM) based on transition metal oxides (TMO), whose operation is based on the change in resistivity of a conductive filament in the oxide material, has attracted a lot of attention in recent years due to its promise of high density, speed, and retention. However, achieving a low power operation and high device-to-device uniformity of the cell resistance states are the major challenges for practical applications of the RRAM technology. While some progress has been made on the understanding of the switching mechanism of TMO memory devices [1], lack of precise control over the filament formation, perceived to be a random process, which inturn introduces randomness into the switching characteristics ofthis class of devices, complicates further progress. This studydemonstrates a forming methodology, which addresses the abovediscussed issues by performing a forming operation under theconstant voltage stress (CVS) condition at lower voltages ratherthan by the conventionally used fast voltage ramp method. Thisapproach is shown to lower the reset current, increase resistivityof the low and high resistive states (LRS, HRS) and improvedevice to device uniformity in the HfO2-based RRAM devices.

2011 - Metal oxide resistive memory switching mechanism based on conductive filament properties [Articolo su rivista]
G., Bersuker; D. C., Gilmer; D., Veksler; P., Kirsch; Vandelli, Luca; Padovani, Andrea; Larcher, Luca; K., Mckenna; A., Shluger; V., Iglesias; M., Porti; M., Nafría
abstract

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament (CF) features controlling TiN/HfO2/TiN resistive memory operations. The leakage current through the dielectric is found to be supported by the oxygen vacancies, which tend to segregate at hafnia grain boundaries. We simulate the evolution of a current path during the forming operation employing the multi-phonon trap-assisted tunneling (TAT) electron transport model. The forming process is analyzed within the concept of dielectric breakdown, which exhibits much shorter characteristic times than that of the electroforming process conventionally employed to describe the formation of the conductive filament. The resulting conductive filament is calculated to produce a non-uniform temperature profile along its length during the reset operation, promoting preferential oxidation of the filament tip. A thin dielectric barrier resulting from the CF tip oxidation is found to control filament resistance in the high resistance state. Field-driven dielectric breakdown of this barrier during the set operation restores the filament to its initial low resistive state. These findings point to the critical importance of controlling the filament resistance characteristics (cross section, stoichiometry) during forming to achieve low power RRAM cell switching.

2011 - Modeling of the forming operation in HfO2-base resistive switching memories [Relazione in Atti di Convegno]
Vandelli, Luca; Padovani, Andrea; Larcher, Luca; G., Bersuker; D., Gilmer; Pavan, Paolo
abstract

This paper presents a novel physical description of the forming process in HfO2-based resistive switching memory devices (RRAM). By taking into consideration a grain boundary-driven trap-assisted electron transport and accounting for the local power dissipation and the associated local temperature increase, which assists defect generation, the model reproduces quantitatively the evolution of the leakage current observed during the forming operation in the RRAM devices. The model statistical capabilities allow reproducing the statistical distribution of the forming voltage, thus providing a powerful tool for the assessment of the feasibility of these devices for high-capacity non-volatile memory mass storage applications

2011 - Modeling strategies for flash memory devices [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

In this paper, we will review the modeling strategies for standard and advanced Flash memory devices based on Floating Gate devices developed by our research group in the last ten years. We will show a complete compact model that includes program/erase and leakage currents that can be used to simulate memory cells in both DC (read operation) and transient conditions (Program/Erase). The same model can be used also for reliability simulations by providing good descriptions of the degradation mechanisms. We will also show the extended model for circuit simulation of NAND strings, modified to account for capacitive coupling effects. Finally, we will show how the same framework can be used to develop a compact model for operations of advanced planar charge-trapping memory devices.

2011 - Modeling the charge transport and degradation in HfO 2 dielectric for reliability improvement and life-time predictions in logic and memory devices [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Vandelli, Luca; Pirrotta, Onofrio; Pavan, Paolo
abstract

HfO2 is currently used in the gate stacks of CMOS logic devices and is widely investigated for its potential application in advanced non-volatile memories such as resistive switching devices (RRAMs). In both applications, the understanding of the physical mechanisms governing the charge transport and the degradation/breakdown (BD) of the dielectric is fundamental to optimize device operation and reliability, and represents the first step toward accurate lifetime predictions. These goals can be achieved through the development of accurate physics-based models linking the microscopic properties of HfO2 to the electrical behavior of the device. We show the model we developed for the charge transport and degradation in HfO2 and its application to logic and memory devices.

2011 - Physical modeling of charge transport and degradation in HfO 2 stacks for logic device and memory applications [Relazione in Atti di Convegno]
Larcher, Luca; Padovani, Andrea; Vandelli, Luca; G., Bersuker
abstract

The understanding of the physical mechanisms responsible of charge transport and degradation in high-k stacks is fundamental for the optimization of advanced logic (MOSFETs) and memory (RRAM, DRAM) devices. In this paper, we present a comprehensive physical model describing the charge transport and the degradation/breakdown processes in the HfO2 layer. This model allows gaining quantitative insights into the physics governing leakage current and degradation processes in HfO2 stacks, reproducing gate current and TDDB statistics

2011 - Threshold Shift Observed in Resistive Switching in Metal-Oxide-Semiconductor Transistors and the Effect of Forming Gas Anneal [Articolo su rivista]
W. H., Liu; K. L., Pey; X., Wu; N., Raghavan; Padovani, Andrea; Larcher, Luca; Vandelli, Luca; M., Bosman; T., Kauerauf
abstract

In this paper the resistive switching mechanism, which is crucial for the operations of RRAM devices, is investigated using HfO2 based MOSFETs. After the SET operation, MOSFETs exhibit a threshold voltage (VT) shift that is found to be closely related to the formation of conductive filaments in the gate oxide. The RESET operation performed through a forming gas anneal treatment is found to have the same effect of applying a reverse polarity gate voltage sweep, as usually done in bipolar switching RRAM devices. After RESET, the gate current and VT measured shift back to their pristine levels, indicating the passivation of oxygen vacancies (forming the conductive path) as the most likely physical mechanism responsible for RRAM’s RESET operation. TEM analysis and physical simulations support these conclusions.

2010 - A Physical Model for Post-Breakdown Digital Gate Current Noise [Articolo su rivista]
Padovani, Andrea; Morassi, Luca; N., Raghavan; Larcher, Luca; L., Wenhu; K. L., Pey; G., Bersuker
abstract

We present a new physical model that enables us to reproduce the digital gate current Random Telegraph Noise (RTN) fluctuations observed in ultra-thin SiON dielectrics in the early stages of post breakdown (BD). Gate current (IG) fluctuations are modeled assuming that some traps in the BD path switch between two unstable configurations, corresponding to neutral and negatively charged O vacancies. Energy levels of the trap considered in simulations here are consistent with values calculated from atomistic simulations. The model allows to reproduce accurately the mean and variation in the IG fluctuations observed on 16Å and 22Å thick SiON gate dielectric at different gate voltages.

2010 - A novel Algorithm for the Solution of Charge Transport Equations in MANOS Devices Including Charge Trapping in Alumina and Temperature Effects [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca
abstract

We present a new algorithm for the exact solutionof the system of equations describing charge trappingand transport across the dielectric stack of nitridebasedcharge trapping memories. The algorithm is implementedin a physical MANOS model accounting fortemperature effects and charge trapping into the Al2O3blocking layer. The model reproduces threshold voltageshifts measured at different temperatures on differentMANOS stacks.

2010 - Analysis of interface-trap effects in inversion-type InGaAs/ZrO2 MOSFETs [Relazione in Atti di Convegno]
Morassi, Luca; Verzellesi, Giovanni; Padovani, Andrea; Larcher, Luca; Pavan, Paolo; D., Veksler; Injo, Ok; G., Bersuker
abstract

Interface-trap effects are analyzed in inversion-type, self-aligned In0.53Ga0.47As and In0.53Ga0.47As/In0.2Ga0.8As MOSFETs with ALD ZrO2 gate dielectric. Interface-trap densities in the order of 1e13 cm-2 eV-1 are required to explain the measured subthreshold slopes. For these Dit values, donor-like interface traps are compatible with threshold-voltage values in the 0-0.15 V range as those observed in these devices. Moreover, the presence of donor-like interface traps can explain the negative threshold-voltage shift induced by the inclusion of the In0.2Ga0.8As cap layer, as the result of the influence of interface traps located at the In0.2Ga0.8As/ZrO2 interface on the inversion channel forming at the In0.53Ga0.47As/In0.2Ga0.8As interface.

2010 - Charge loss in TANOS devices caused by Vt sensing measurements during retention [Relazione in Atti di Convegno]
H., Park; G., Bersuker; D., Gilmer; K. Y., Lim; M., Jo; H., Hwang; Padovani, Andrea; Larcher, Luca; Pavan, Paolo; W., Taylor; P. D., Kirsch
abstract

In TANOS stuctures in retention, the major decrease in theprogrammed threshold voltage is found to be caused by the Vtsensing (IdVg measurements) rather than by intrinsic charge loss(when no bias is applied). This Vt decrease can be understoodwithin the process of the temperature-activated charge transportthrough the Al2O3 blocking oxide. The charge loss can beminimized when Vt sensing time is decreased down to microseconds. Blocking oxides engineered by adding a thin SiO2 layerat the SiN/AlO interface demonstrate significant suppression of thecharge loss.

2010 - Experimental assessment of electrons and holes in erase transient of TANOS and TANVaS memories [Articolo su rivista]
A., Suhane; A., Arreghini; G., Van den bosch; Vandelli, Luca; Padovani, Andrea; L., Breuil; Larcher, Luca; K., De Meyer; J., Van Houdt
abstract

We present carrier separation experiments based on direct charge measurement to assess the contributions of electronsand holes to the erase transient of TANOS-like nonvolatilememories. The role of the different carrier species is analyzed asa function of the erase voltage and of the charge configurationat the initial programmed state. We extend the analysis toBand Engineered tunneling barriers, demonstrating that theperformance improvement in these devices lays more in anenhancement of the hole current rather than of the electron one.

2010 - Fundamental reliability issues of advanced charge-trapping Flash memory devices [Relazione in Atti di Convegno]
Larcher, Luca; Padovani, Andrea
abstract

The basic reliability issues of Charge Trapping (CT) Flash memory devices will be discussed from a physical perspective, highlighting the reliability implications of process and technology innovations introduced to sustain the uninterrupted device scaling down. We will focus on the reliability issues related to the charge localization inside the trapping layer and the high-κ band-gap engineered stacks introduced to implement both tunnel and blocking dielectrics. We will describe the physical mechanisms responsible of reliability degradation (data retention, array disturbs, endurance), discussing briefly the issues related to ultra-scaled and vertically stacked 3D Flash memory devices.

2010 - Gate Leakage Current Reduction in Two-Step Processed High-k Dielectrics for Low Power Applications [Relazione in Atti di Convegno]
G., Bersuker; D., Heh; J., Huang; C. S., Park; Padovani, Andrea; Larcher, Luca; P., Kirsch; R., Jammy
abstract

Reduction of the gate leakage current in nMOS high-k devices is demonstrated by an engineered two-step deposited Hf-based high-k dielectric film. The electrical characteristics and reliability of the devices fabricated using the proposed two-step and conventional one-step high-k gate stacks are shown to be comparable. The lower leakage current is attributed to the misalignment of the grain boundaries in the multi-layer high-k dielectrics.

2010 - High-k related reliability issues in advanced Non-Volatile Memories [Articolo su rivista]
Larcher, Luca; Padovani, Andrea
abstract

In the last decade, important technology solutions have been proposed to scale down Flash memory devices beyond the 30nm node. The most important innovations are the introduction of charge trapping layer and high- materials in both bottom and top dielectric stacks, which allows reducing both the bottom dielectric thickness and the Program/Erase voltages, while maintaining the P/E performances and (theoretically) without degrading the memory device reliability. Theoretical advantages and reliability issues of these important innovations will be reviewed by addressing physical mechanisms responsible of reliability degradation. In particular, charge trapping layers introduced in place of the poly-silicon FG will be discussed highlighting the reliability consequences of the discrete charge storage. Similarly, theoretical advantages and reliability issues of bottom and top dielectric stacks incorporating high- materials (used mainly also to implement band-gap engineered barriers) will be carefully analyzed, relating high- material properties to memory device performances and reliability.

2010 - Investigation of the impact of H-related defects in Al2O3 blocking layer of charge-trap memories by atomistic simulations and device physical modeling [Relazione in Atti di Convegno]
G., Molas; L., Masoero; P., Blaise; Padovani, Andrea; J. P., Colonna; E., Vianello; M., Bocquet; E., Nowak; M., Gasulla; O., Cueto; H., Grampeix; F., Martin; R., Kies; P., Brianceau; M., Gély; A. M., Papon; D., Lafond; J. P., Barnes; C., Licitra; G., Ghibaudo; Larcher, Luca; S., Deleonibus; B., De Salvo
abstract

In this work, we use atomistic simulation, consolidated by a detailed Al2O3 physico-chemical material analysis, to investigate the origin of traps in Al2O3 (in particular, Al- or O-vacancies and H-interstitials). It is shown that the leakage currents through Al2O3 layers, with different post-deposition anneals, are strictly correlated to the H content. Then, for the first time at our knowledge, the hydrogen-based trap features estimated by quantum simulations are introduced in a TANOS device simulator. A very good agreement is obtained between model and device experimental data, allowing for a clear understanding of the role of alumina H content on the retention characteristics of charge-trap memories.

2010 - Investigation of the role of H-related defects in Al2O3 blocking layer on charge-trap memory retention by atomistic simulations and device physical modelling [Relazione in Atti di Convegno]
Molas, G.; Masoero, L.; Blaise, P.; Padovani, A.; Colonna, J. P.; Vianello, E.; Bocquet, M.; Nowak, E.; Gasulla, M.; Cueto, O.; Grampeix, H.; Martin, F.; Kies, R.; Brianceau, P.; Gely, M.; Papon, A. M.; Lafond, D.; Barnes, J. P.; Licitra, C.; Ghibaudo, G.; Larcher, L.; Deleonibus, S.; De Salvo, B.
abstract

In this work, we use atomistic simulation, consolidated by a detailed Al2O3 physico-chemical material analysis, to investigate the origin of traps in Al2O3 (in particular, Al- or O-vacancies and H-interstitials). It is shown that the leakage currents through Al2O3 layers, with different post-deposition anneals, are strictly correlated to the H content. Then, for the first time at our knowledge, the hydrogen-based trap features estimated by quantum simulations are introduced in a TANOS device simulator. A very good agreement is obtained between model and device experimental data, allowing for a clear understanding of the role of alumina H content on the retention characteristics of charge-trap memories. ©2010 IEEE.

2010 - Investigation of trapping/detrapping mechanisms in Al2O3 electron/hole traps and their influence on TANOS memory operations [Relazione in Atti di Convegno]
Larcher, Luca; Padovani, Andrea; Vincenzo della, Marca; Pavan, Paolo; Bertacchini, Alessandro
abstract

The purpose of this work is to investigate the physics of electron/hole trapping/detrapping mechanisms in Al2O3. Combining I-V and C-V measurements with a physical model we derive the energy levels of electron/hole traps and the location of electron/hole charge. The influence of electron/hole alumina traps on TANOS operations and reliability is investigated.

2010 - Leakage Current in TiN/HfO2/TiN MIM Capacitors and Degradation due to Electrical Stress [Relazione in Atti di Convegno]
S., Cimino; Padovani, Andrea; Larcher, Luca; V. V., Afanas’Ev; H. J., Hwang; Y. G., Lee; M., Jurczac; D., Wouters; B. H., Lee; H., Hwang; L., Pantisano
abstract

Metal Insulator Metal (MIM) capacitors are widely used in the electronic industry for DRAM as well as for analog applications. Defects in dielectric structures are very important as they control not only gate leakage and power consumption but, also, device noise and lifetime. Physical and electrical characteristics of TiN/HfO2/TiN capacitors have been investigated aiming at the study of defects and defect energy position in HfO2 on TiN.

2010 - Leakage current in TiN/HfO2/TiN MIM capacitors and degradation due to electrical stress [Relazione in Atti di Convegno]
S., Cimino; Padovani, Andrea; Larcher, Luca; V. V., Afanas’Ev; H. J., Hwang; Y. G., Lee; M., Jurczac; D., Wouters; B. H., Lee; H., Hwang; L., Pantisano
abstract

Electrical characteristics of TiN/HfO2/TiN capacitors have been investigated by means of leakage current and Random Telegraph Noise measurements. Trap assisted transport simulation allowed the extraction of relevant parameters like trap density and trap energy position. The extracted parameters show striking similarities with those reported for HfO2 deposited on a Si surface (i.e., MOSFET applications). Additionally, even low bias Constant Voltage Stress was found to induce leakage current degradation on current vs voltage characteristics, preferentially at low voltage. The leakage current degradation is explained by preexisting defect precursors or by involvement of hydrogen in creating defects as observed on thermal SiO2 layers.

2010 - Mechanism of high-k dielectric-induced breakdown of interfacial SiO2 layer [Relazione in Atti di Convegno]
G., Bersuker; D., Heh; C. D., Young; Morassi, Luca; Padovani, Andrea; Larcher, Luca; K. S., Yew; Y. C., Ong; D. S., Ang; K. L., Pey; W., Taylor
abstract

A mechanism of degradation and breakdown in highk/metal gate transistors was investigated. Based on the electricaltest, physical analysis, and modeling results, we propose that thebreakdown path formation/evolution in the interfacial SiO2 layeris associated with the growth of an oxygen-deficient filamentfacilitated by the grain boundaries of the overlaying high-k film.The model allows reproducing SILC temperature dependencyand its exponential increase from the fresh through soft andprogressive breakdown phases.

2010 - Metal oxide RRAM switching mechanism based on conductive filament microscopic properties [Relazione in Atti di Convegno]
G., Bersuker; D. C., Gilmer; D., Veksler; J., Yum; H., Park; S., Lian; Vandelli, Luca; Padovani, Andrea; Larcher, Luca; K., Mckenna; A., Shluger; V., Iglesias; M., Porti; M., Nafría; W., Taylor; P. D., Kirsch; R., Jammy
abstract

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament features controlling TiN/HfO2/TiN resistive memory operations. The forming process is found to define the filament geometry, which in turn determines the temperature profile and, consequently, the switching characteristics. The findings point to the critical importance of controlling filament dimensions during the forming process (polarity, max current/voltage, etc.).

2010 - Modeling Temperature Dependency (6 - 400K) of the Leakage Current Through the SiO2/High-K Stacks [Relazione in Atti di Convegno]
Vandelli, Luca; Padovani, Andrea; Larcher, Luca; G., Bersuker; R. G., Southwick III; W. B., Knowlton
abstract

We investigate the mechanism of the gate leakagecurrent in the Si/SiO2/HfO2/TiN stacks in a wide temperaturerange (6 – 400 K) by simulating the electron transport using amulti-phonon trap assisted tunneling model. Good agreementbetween simulations and measurements allows indentifying thedominant physical processes controlling the temperaturedependency of the gate current. In depletion/weak inversion, thecurrent is limited by the supply of carrier. In strong inversion,the electron-phonon interaction is found to be the dominantfactor determining the current voltage and temperaturedependencies. These simulations allowed to extract importantdefect parameters, e.g. the trap relaxation energy and phononeffective energy, which defines the defect atomic structure.

2010 - Role of Holes and Electrons During Erase of TANOS Memories: Evidences for Dipole Formation and its Impact on Reliability [Relazione in Atti di Convegno]
Vandelli, Luca; Padovani, Andrea; Larcher, Luca; Antonio, Arreghini; Geert Van den, Bosch; Malgorzata, Jurczak; Jan Van, Houdt; Vincenzo Della, Marca; Pavan, Paolo
abstract

The systematic investigation of the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations is reported for the first time. We determined a dominance of electrons back-tunneling in the first part of the transient, and dominance of holes in the second part. Good agreement is reached between experimental and simulated data. In addition we demonstrate for the first time the formation of a vertical charge dipole in TANOS devices, whose polarity depends on the P/E operation sequence. This dipole severely affects the program and erase performances and the retention of mild programmed and erased states, which is a concern especially for multilevel applications.

2010 - SET switching effects on PCM endurance [Relazione in Atti di Convegno]
V., Della Marca; F., Carboni; Larcher, Luca; Padovani, Andrea; Pavan, Paolo
abstract

In this paper we report results on PCM endurance failure characterization. We show that endurance failure is related to SET pulse features and we analyze and model SET operation to obtain a better understanding and improve endurance performance. Results give interesting insights on the crystallization process of GST material. SET obeys to a constant energy law. Fast SET pulses require high power; slow SET pulses can be implemented in low power applications. Results may be used for optimized SET/RESET operation to achieve better endurance.

2010 - Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics [Relazione in Atti di Convegno]
Morassi, Luca; Padovani, Andrea; Verzellesi, Giovanni; D., Veksler; I., Ok; G., Bersuker
abstract

In this paper, we use 2D numerical device simulations [Sentaurus Device, Synopsys Inc.] to investigate the impact of interface traps on the electrical characteristics of MOSFETs and MOSHEMTs with InGaAs channel and high-k gate dielectrics. More specifically, the following two technologies are taken into consideration: A) self-aligned inversion-type InGaAs/ZrO2 MOSFETs; B) implant-free InGaAs/Al2O3 MOSHEMTs.

2010 - Temperature Effects on Metal-Alumina-Nitride-Oxide-Silicon Memory Operations [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; D., Heh; G., Bersuker; V., Dellamarca; Pavan, Paolo
abstract

We present a detailed investigation of temperature effects on the operation of TaN/Al2O3 / Si3N4 /SiO2 / Si (TANOS) memory devices. We show that not only retention but also program and erase operations are affected significantly by temperature. Using a large set of experimental data and simulations on a variety of TANOS stacks, we show that the temperature dependence of TANOS program and erase operations can be explained by accounting for that the alumina dielectric constant increases by 20%–25% over a 125 K temperature range.

2009 - A Novel Fluorine Incorporated Band Engineered (BE) Tunnel (SiO2/ HfSiO/ SiO2) TANOS with Excellent Program/Erase & Endurance to 10^5 Cycles [Relazione in Atti di Convegno]
S., Verma; G., Bersuker; D. C., Gilmer; Padovani, Andrea; P., Hokyung; A., Nainani; D., Heh; J., Huang; J., Jiang; K., Parat; P. D., Kirsch; Larcher, Luca; Hsing Huang, Tseng; K. C., Saraswat; R., Jammy
abstract

We demonstrate for the first time a fluorine incorporated band- engineered (BE) tunnel oxide (SiO2/HfSiO/SiO2) TANOS with excellent program / erase (P/E) characteristics and endurance to 105 cycles. Incorporating fluorine in the tunnel dielectric improves Si/SiO2 interface resulting in excellent endurance of nearly constant over 3 V P/E window for at least 105 cycles. Fluorine also reduces interface state generation during retention by ~20%. Furthermore, Fluorine passivates bulk traps leading to as much as ~10times higher charge to breakdown (Qbd) and ~10-50times lower interface state density (Dit). Fluorine passivation for BE-TANOS is significant because it improves reliability assisting implementation of TANOS flash NVM beyond the 20 nm node.

2009 - A technique to extract high-k IPD stack layer thicknesses from C-V measurements [Articolo su rivista]
Larcher, Luca; Pavan, Paolo; Padovani, Andrea; G., Ghidini
abstract

We propose in this letter a simple technique based on C-V measurements which allows to estimate the thicknesses of SiOX and high-k layers of IPD stacks. We apply this technique to IPD Al2O3-based stacks for floating gate memory applications, finding a good agreement with TEM measurements. In addition, simulation results are provided to demonstrate the correctness of the basic assumption of this technique.

2009 - Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing [Relazione in Atti di Convegno]
Morassi, Luca; Larcher, Luca; L., Pantisano; Padovani, Andrea; R., Degreave; M. B., Zahid; B. J., O'Sullivan
abstract

This paper presents an original approach for material studies for memory devices where the degree of intermixing between the high-k and interfacial SiO2 is explicitly quantified experimentally. Using calibrated leakage simulation the importance of intermixing is verified independently together with the conduction mechanism. The implication for NVM reliability are profound and will be discussed toward retention mechanisms and used to optimize retention margins for NVM memories.

2009 - Connecting electrical and structural dielectric characteristics [Relazione in Atti di Convegno]
G., Bersuker; D., Veksler; C. D., Young; H., Park; Morassi, Luca; Padovani, Andrea; Larcher, Luca; W., Taylor; P. D., Kirsch; R., Jammy
abstract

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2009 - Modeling TANOS Memory Program Transients to Investigate Charge Trapping Dynamics [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; D., Heh; G., Bersuker
abstract

A novel physics-based drift-diffusion model of TANOS program transients is employed to investigate electron trapping and detrapping dynamics in the nitride trapping layer. Trapping process is found to be independent from the energy of injected electrons, while detrapping is dominated by trap-to-band tunneling. Modeling of the trapped charge evolution during program transients allows to extract physical characteristics of the traps and provides useful information for the optimization of TANOS memories.

2009 - Understanding endurance degradation in Flash memory through transconductance measurement [Relazione in Atti di Convegno]
S., Verma; G., Bersuker; D. C., Gilmer; Padovani, Andrea; H., Park; A., Nainani; J., Huang; K., Parat; P. D., Kirsch; Larcher, Luca; H. H., Tseng; K. C. Saraswat R., Jammy
abstract

Endurance degradation is a limitation for implementing futurescaled flash memory devices. This degradation is mainly attributableto Si/SiO2 interface traps generated during program/erase (P/E) stress rather than fixed charges in the bulk oxide. In this work, we use Gm (transconductance) to monitor the interface degradation. Wereport that interface defect generation is highest during erase operation. In addition to the interface, hole & electron tunnelingprobability seem crucial to degradation during erase. Fluorine incorporation in tunnel stack is found to reduce Gm degradationsuggesting improved interface.

2008 - Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric [Relazione in Atti di Convegno]
G., Bersuker; D., Heh; C., Young; H., Park; P., Khanal; Larcher, Luca; Padovani, Andrea; P., Lenahan; J., Ryan; B. H., Lee; H., Tseng; R., Jammy
abstract

We apply a systematic approach to identify a high-k/metal gate stack degradation mechanism. Our results demonstrate that the SiO2 interfacial layer controls the overall degradation and breakdown of the high-k gate stacks stressed in inversion. Defects contributing to the gate stack degradation are associated with the high-k/metal-induced oxygen vacancies in the interfacial layer.

2008 - Feasibility of SIO2/Al2O3 tunnel dielectric for future Flash memories generations [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; S., Verma; Pavan, Paolo; P., Majhi; P., Kapur; K., Parat; G., Bersuker; K., Saraswat
abstract

In this paper, we investigate the feasibility of SiO2/Al2O3 stack tunnel dielectric for future Flash memory generations using statistical leakage current simulations. We show that the statistical Monte Carlo (MC) simulator we employed reproduces accurately leakage currents measured on SiO2/Al2O3 dielectric capacitors. Exploiting its statistical capabilities, we calculate leakage current distributions in Flash memory retention conditions. We show that the high defectiveness of AI2O3 stacks strongly reduces the potential improvement of Flash retention due to the introduction of AI2O3 tunnel dielectric.

2008 - Hole Distributions in Erased NROM Devices: profiling method and effects on reliability [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

The NROM-cell concept has been introduced as a promising technology to replace Flash nonvolatile memory devices also in embedded products, owing to its intrinsic 2-b/cell operation and better endurance. However, the presence of physically sepa- rated electron and hole distributions generated by program and erase operations is reported to be one of the main causes of the device’s retention degradation. Therefore, a deep knowledge of the features and evolution of the nitride-storage charge is crucial for reliability, cell optimization, future scalability, and multilevel oper- ation. In this scenario, the purpose of this paper is twofold, which is as follows: 1) to introduce a combined simulative experimental method allowing profiling hole distribution in devices erased with different bias conditions and 2) to monitor through this technique the evolution of the nitride charge with cycling, correlating it to the degradation of memory reliability after cycling.

2008 - Modeling NAND Flash Memories for IC Design [Articolo su rivista]
Larcher, Luca; Padovani, Andrea; Pavan, Paolo; P., Fantini; A., Calderoni; A., Mauri; A., Benvenuti
abstract

In this letter, we present a compact model of NAND Flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simula- tion of NAND Flash memories with a limited computational effort, taking into account capacitive coupling effects which will become extremely important in future technology generations. This model is a very valuable tool for IC designers to optimize NVM circuits, particularly in multilevel applications.

2008 - On the RESET-SET transition in Phase Change Memories [Relazione in Atti di Convegno]
G., Puzzilli; F., Irrera; Padovani, Andrea; Pavan, Paolo; Larcher, Luca; A., Arya; DELLA MARCA, Vincenzo; A., Pirovano
abstract

We characterize SET operation in Phase Change Memories. A measurement procedure aiming to investigate resistance transition from amorphous to crystalline states is shown. Results give interesting insights on the crystallization process of GST material and a simple model is introduced. Crystallization process obeys to a constant energy law. Fast SET pulses require high power; slow SET pulses can be implemented in low power applications. Results may be used for an optimized design of memory cell operating conditions.

2008 - Statistical modeling of leakage currents through SiO2/high- κ dielectrics stacks for non-volatile memory applications [Relazione in Atti di Convegno]
Padovani, A.; Larcher, L.; Verma, S.; Pavan, P.; Majhi, P.; Kapur, P.; Parat, K.; Bersuker, G.; Saraswat, K.
abstract

We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-kappa dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-kappapsilas traps on leakage current distribution for flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-kappa tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-kappa tunnel stacks and to improve technology reliability issues related to flash memory applications.

2007 - Dielectric Reliability for Future Logic and Non-Volatile Memory Applications: a Statistical Simulation Analysis Approach [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; A., Chimenton; Pavan, Paolo; P., Olivo
abstract

In this paper, we present a physically-based Monte-Carlo (MC) model reproducing the leakage current flowing across typical dielectric layers (SiO2, high-k) used in ULSI technologies. Simulations will be shown to predict accurately currents measured on MOSFETs, large area MOS capacitor, and tunnel oxides of Flash memories after electrical and radiation stresses. Statistical aspects related to leakage current and threshold voltage are reproduced correctly, allowing worst case corner prediction, necessary to assess dielectric damaging effects on logic circuits and non-volatile memory operation.

2007 - Hole Distributions in NROM Devices: Profiling Technique and Correlation to Memory Retention [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

In this work, we presented a new technique to profile hole distribution in NROM devices. The evolution of the nitride charge in cycled cells was monitored. The key role played by holes in NROM retention degradation was identified. Electron injection far from the junction and VT drift in erased NROM cells are successfully explained.

2007 - ID-VGS Based Tools to Profile Charge Distributions on NROMTM Memory Devices [Articolo su rivista]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo; L., Avital; I., Bloom; B., Eitan
abstract

The NROM cell concept has been introduced as a promising technology to replace Flash non-volatile memory devices also in embedded products, thanks to its intrinsic two-bits/cell operation and better endurance. However, the presence of physically separated electron and hole distributions generated by program and erase operations is reported to be one of the main causes of device’s retention degradation. Therefore, a deep knowledge of the features and evolution of the nitride storage charge is crucial for reliability, cell optimization, future scalability and multi-level operation. In this scenario, the purpose of this paper is twofold: 1) to introduce a combined simulative-experimental method allowing profiling hole distribution in devices erased with different bias conditions; 2) to monitor through this technique the evolution of the nitride charge with cycling, correlating it to the degradation of memory reliability after cycling.

2007 - Modeling NAND Flash memories for circuit simulations [Relazione in Atti di Convegno]
Larcher, Luca; Padovani, Andrea; I., Rimmaudo; Pavan, Paolo; A., Calderoni; G., Molteni; F., Gattel; P., Fantini
abstract

In this paper, we will present the basic structure and the parameter extraction procedure for a compact model of a NAND Flash memory string working in Spice-like circuit simulators. To the author knowledge, this is the first Spice-like model of a NAND Flash memory string. This model is modular and simple to be implemented. It will allow accurately reproducing both DC and transient behavior of NAND Flash memories without increasing computational effort, thus becoming an indispensable tool for designers to optimize circuits especially in multi-level applications.

2007 - Monte-Carlo Simulations of Flash Memory Array Retention [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; A., Chimenton; Pavan, Paolo
abstract

One of the major scalability limitations of flash memories is anomalous SILC, which strongly endangers device reliability and data retention. Therefore, an accurate evaluation of SILC statistics on large arrays is crucial for reliability predictions and new Flash technology development. In the last years, oxide leakage currents were deeply investigated and modeled, neglecting SILC statistics and effects on large Flash arrays. More recently, analytical models relating Flash statistical threshold voltage (VT) distributions to defect statistics and leakage current were proposed. However, these models rely on several simplifying assumptions such as the equivalent cell concept and an uniform defect population. Still, these models do not account for the initial VT distribution and neglect the role played by trap energy and effective field. In this scenario, the purpose of this paper is to present a Monte-Carlo (MC) simulator reproducing flash VT distribution, which overcomes the above model limitations. We will show that this model can be used to 1) investigate effects of defect features and technology parameters on VT distribution, and 2) analyze the impact of temperature and voltage accelerated stresses on final VT distribution.

2007 - Statistical Methodologies for Integrated Circuits Design [Relazione in Atti di Convegno]
Padovani, Andrea; A., Chimenton; P., Olivo; P., Fantini; L., Vendrame; S., Mennillo
abstract

The continuous scaling of physical dimensions has strongly increased circuit performance variability and the traditional corner-case methodology is becoming unreliable. As a consequence, there is an urgent need for new and more accurate statistical models. In this scenario, the purpose of this paper is twofold: 1) to give the reader the basic concepts of statistical modeling, and 2) to discuss a viable statistical approach that could be adopted into a traditional IC design flow for the next technology generations.

2006 - Profiling charge distribution in NROM devices [Relazione in Atti di Convegno]
Padovani, Andrea; Larcher, Luca; Pavan, Paolo
abstract

NROM memory cells are proposed as one of the most promising non-volatile memories. Issues on scaling and endurance have risen due to the presence of both electrons and holes, for the control of their relative position and spread in the charge trapping material. Therefore, a deeper analysis of the injected-charge distribution region is very important for program/erase bias optimization, reliability prediction and future scaling. In this paper, we introduce and discuss two tools, based on subthreshold slope and temperature effects, able to correctly estimate program charge distribution features from simple ID - VGS measurements

2006 - Temperature Monitor: a New Tool to Profile Charge Distribution in NROMTM Memory Devices [Relazione in Atti di Convegno]
L., Avital; Padovani, Andrea; Larcher, Luca; I., Bloom; R., Arie; Pavan, Paolo; B., Eitan
abstract

NROM memory cells are proposed as one of the most promising non-volatile memories. Issues on scaling and endurance have risen due to the presence of both electrons and holes for the control of their relative position and spread in the charge trapping material. In this paper, we present a new characterization tool able to sense charge distribution features in different program/erase conditions that can be efficiently used for program/erase bias optimization and reliability predictions. This new tool exploits temperature effects on ID-VGS current measurements